SDRSDRAM控制器白皮书中英文对照版本.docx

1、SDRSDRAM控制器白皮书中英文对照版本SDR SDRAM 控制器白皮书 中英文对照版翻译：合肥工业大学 检测技术研究所 彭良清（peng6602） 日期：2004/4/24原文：IntroductionThe single data rate (SDR) synchronous dynamic random access memory (SDRAM) controller provides a simplified interface to industry standard SDR SDRAM. The SDR SDRAM Controller is available in eithe

2、r Verilog HDL or VHDL and is optimized for the Altera APEX architecture. The SDR SDRAM Controller supports the following features: Burst lengths of 1, 2, 4, or 8 data words CAS latency of 2 or 3 clock cycles 16-bit programmable refresh counter used for automatic refresh 2-chip selects for SDRAM devi

3、ces Supports the NOP, READA, WRITEA, AUTO_REFRESH, PRECHARGE, ACTIVATE, URST_STOP,and LOAD_MR commands Support for full-page mode operation Data mask line for write operations PLL to increase system performance Support for data-path widths of 16, 32, and 64 bitsFigure 1 shows a system-level diagram

4、of the SDR SDRAM Controller.SDRAM OverviewSDRAM is high-speed dynamic random access memory (DRAM) with a synchronous interface. The synchronous interface and fully-pipelined internal architecture of SDRAM allows extremely fast data rates if used efficiently. Internally, SDRAM devices are organized i

5、n banks of memory, which are addressed by row and column. The number of row- and column-address bits and the number of banks depends on the size of the memory. SDRAM is controlled by bus commands that are formed using combinations of the RASN, CASN, and WEN signals. For instance, on a clock cycle wh

6、ere all three signals are high, the associated command is a no operation (NOP). A NOP is also indicated when the chip select is not asserted. Table 1 shows the standard SDRAM bus commands.表1. SDRAM 总线命令命 令缩 写RASNCASNWENNo operation NOPHHHActive ACTLHHRead RDHLHWrite WRHLLBurst terminate BTHHLPrechar

7、ge PCHLHLAutorefresh ARFLLHLoad mode register LMRLLLSDRAM banks must be opened before a range of addresses can be written to or read from. The row and bank to be opened are registered coincident with the ACT command. When a bank is accessed for a read or a write it may be necessary to close the bank

8、 and re-open it if the row to be accessed is different than the row that is currently opened. Closing a bank is done with the PCH command.SDRAMThe primary commands used to access SDRAM are RD and WR. When the WR command is issued, the initial column address and data word is registered. When a RD com

9、mand is issued, the initial address is registered. The initial data appears on the data bus 1 to 3 clock cycles later. This is known as CAS latency and is due to the time required to physically read the internal DRAM core and register the data on the bus. The CAS latency depends on the speed of the

10、SDRAM and the frequency of the memory clock. In general, the faster the clock, the more cycles of CAS latency are required. After the initial RD or WR command, sequential read and writes continue until the burst length is reached or a BT command is issued. SDRAM memory devices support burst lengths

11、of 1, 2, 4, or 8 data cycles. The ARF is issued periodically to ensure data retention. This function is performed by the SDR SDRAM Controller and is transparent to the user.Functional DescriptionTable 2 shows the SDR SDRAM Controller interface signals. All signals are synchronous to the system clock

12、 and outputs are registered at the SDR SDRAM Controllers outputs.信号名称激活电平I/O 描述CLK 时钟NAInput系统时钟RESET_N 复位Low Input 系统复位ADDRASIZE-1:0 存储器地址NAInput 读或者写时的存储器地址，地址宽度由ASIZE.设置CMD2:0 命令NA Input 命令请求CMDACK 命令应答HighOutput 命令请求的响应DATAINDSIZE-1:0 输入数据NA Input 输入数据总线，宽度由DSIZE设置DATAOUTDSIZE-1:0 输出数据NA Output

13、数据数据总线，宽度由DSIZE设置DM(DSIZE/8)-1:0 数据屏蔽HighInput Masks individual bytes during data writeSA11:0 地址总线NA OutputSA11:0信号在ACT命令发出时锁存到行地址中，SAn:0在RD/WR命令期间锁存到列地址中，其中“n”值取决于使用的SDRAM容量，SA10信号在PCH命令时被采样，该信号决定是否对所有存储体还是对指定存储器（由信号BA1:0决定）进行预充电。地址输出在LMR命令时提供操作码。BA1:0 体选地址NA Output 该信号决定了在ACT, RD, WR, 或PCH 命令时，选择那

14、个存储体。CS_N1:0片选Low Output SDRAM chip selects.SDRAM片选信号，CKE 时钟使能High Output SDRAM 的CKE信号输入RAS_N 行地址选通Low Output SDRAM 命令输入CAS_N 列地址选通Low Output SDRAM 命令输入WE_N 写使能Low Output SDRAM 命令输入.DQDSIZE-1:0数据总线NAI/OSDRAM 数据总线DQM(DSIZE/8)-1:0 数据屏蔽写HighOutputSDRAM 数据屏蔽，在数据写器件屏蔽单个字节数据NA: SDRAM Controller Command In

15、terfaceThe SDR SDRAM Controller provides a synchronous command interface to the SDRAM and several control registers.Table 3 shows the commands, which are described in following sections. The following rules apply to the commands: All commands, except NOP, are driven by the user onto CMD2:0; ADDR and

16、 DATAIN are set appropriately for the requested command. The controller registers the command on the next rising clock edge To acknowledge the command the controller asserts CMDACK for one clock period For READA or WRITEA commands, the user should start receiving or writing data on DATAOUT and DATAI

17、N The user must drive NOP onto CMD2:0by the next rising clock edge after CMDACK is asserted表3. 接口命令CommandValueDescriptionNOP 000b 空操作READA 001b 带自动预充电的SDRAM 读操作WRITEA010b 带自动预充电的SDRAM 写操作REFRESH 011b SDRAM 自动刷新PRECHARGE 100b对SDRAM 所有存储体预充电LOAD_MODE 101b SDRAM 模式寄存器装入r.LOAD_REG1 110b 装入控制器配置寄存器LOAD_

18、REG2 111b 装入控制器刷新周期寄存器NOP CommandNOP is a no operation command to the controller. When NOP is detected by the controller, it performs a NOP in the following clock cycle. A NOP must be issued the following clock cycle after the controller has acknowledged a command. The NOP command has no affect on S

19、DRAM accesses that are already in progress.READA CommandThe READA command instructs the SDR SDRAM Controller to perform a burst read with auto-precharge to the SDRAM at the memory address specified by ADDR. The SDR SDRAM Controller issues an ACTIVATE command to the SDRAM followed by a READA command.

20、 The read burst data first appears on DATAOUT (RCD + CL + 2) after the SDR SDRAM Controller asserts CMDACK. During a READA command the user must keep DM low. When the controller is configured for full-page mode, the READA command becomes READ (READ without auto-precharge). Figure 2 shows an example

21、timing diagram for a READA command. The following sequence describes the general operation of the READA command: The user asserts READA, ADDR and DM The SDR SDRAM Controller asserts CMDACK to acknowledge the command and simultaneously starts issuing commands to the SDRAM devices One clock after CMDA

22、CK is asserted, the user must assert NOP The CMDACK presents the first read burst value on DATAOUT, the remainder of the read bursts follow every clock cycleWRITEA CommandThe WRITEA command instructs the SDR SDRAM Controller to perform a burst write with auto-precharge to the SDRAM at the memory add

23、ress specified by ADDR. The SDR SDRAM Controller will issue an ACTIVATE command to the SDRAM followed by a WRITEA command. The first data value in the burst sequence must be presented with the WRITEA and ADDR address. The host must start clocking data along with the desired DM values into the SDR SD

24、RAM Controller (tRCD 2) clocks after the SDR SDRAM Controller has acknowledged the WRITEA command. See a SDRAM data sheet for how to use the data mask lines DM/DQM. When the SDR SDRAM Controller is in the full-page mode WRITEA becomes WRITE (write without auto-precharge). Figure 3 shows an example t

25、iming diagram for a WRITEA command. The following sequence describes the general operation of a WRITEA command: The user asserts WRITEA, ADDR, the first write data value on DATAIN, and the desired data mask value on DM The SDR SDRAM Controller asserts CMDACK to acknowledge the command and simultaneo

26、usly starts issuing commands to the SDRAM devices One clock after CMDACK was asserted, the user asserts NOP on CMD The user clocks data and data mask values into the SDR SDRAM Controller through DATAIN and DMREFRESH CommandThe REFRESH command instructs the SDR SDRAM Controller to perform an ARF comm

27、and to the SDRAM. The SDR SDRAM Controller acknowledges the REFRESH command with CMDACK. Figure 4 shows an example timing diagram of the REFRESH command. The following sequence describes the general operation of a REFRESH command: The user asserts REFRESH on the CMD input The SDR SDRAM Controller as

28、serts CMDACK to acknowledge the command and simultaneously starts issuing commands to the SDRAM devices The user asserts NOP on CMDPRECHARGE CommandThe PRECHARGE command instructs the SDR SDRAM Controller to perform a PCH command to the SDRAM. The SDR SDRAM Controller acknowledges the command with C

29、MDACK. The PCH command is also used to generate a burst stop to the SDRAM. Using PRECHARGE to terminate a burst is only supported in the full-page mode. Note that the SDR SDRAM Controller adds a latency from when the host issues a command to when the SDRAM sees the PRECHARGE command of 4 clocks. If

30、a full-page read burst is to be stopped after 100 cycles, the PRECHARGE command must be asserted (4 + CL 1) clocks before the desired end of the burst (CL 1 requirement is imposed by the SDRAM devices). So if the CAS latency is 3, the PRECHARGE command must be issued (100 3 1 4) = 92 clocks into the

31、 burst. Figure 5 shows an example timing diagram of the PRECHARGE command. The following sequence describes the general operation of a PRECHARGE command: The user asserts PRECHARGE on CMD The SDR SDRAM Controller asserts CMDACK to acknowledge the command and simultaneously starts issuing commands to the SDRAM devices The user asserts NOP on CMDLOAD_MODE