SMT高级工程师教案测试.docx

1、SMT高级工程师教案测试SMT 高级工程师教案6SMT测试ATE 工程师应注意及准备事项：1.当拿到R/D CAD FILES 时，请在A-TEST导入时分析该被测试之TEST ABILITY2.在B-TEST 导入ATE测试时，应注意版本变更之零件，规格；并分析下列资料： 名 称 数 量A. PCB CAD FILES (NEW VER) 1B. BOM 1C. ARTWORK 1D. CIRCUIT 1E. BEAR BOARD 1-2F. FUNCTION M/B 2-33.B-TEST后提出TEST ABILITY报告.A. 列出A-TEST & B-TEST之异差B. 列出那些零件须

2、加测试点及注意事项C. 列出治具要求之注意事项D. 列出LAYOUT TEST PAD 及测试针之规格及注意事项E. 其它R/D设计须附合治具程控之要求ATE 工程师应注意及准备事项：1. R/D在LAYOUT时之节点至少要有一测试点(TEST PAD)2. 线路途的每一测试点(TEST PAD)，间距至少75 MIL以上3. 手插零件不需加测试点，但如果是CONNECTOR很密之零件视需要加测试点.4. CHIP除了空脚外，其余各脚均需加测试点.5. 如果是单面之被测试时，测试点要均匀分布于测试板.6. 如果是双面之被测试时，测试点尽量LAYOUT在焊锡面.7. 测试点附近之零件高度应小于0

3、.255IN (视产品而定)8. 测试点周围0.018IN内不可有测试或零件9. PCB 边缘0.125 IN内不可有测试点10.测试点到另一测试点不可小于0.083IN.125.125.125PCB DEIGES.1250.08272.1mm(82.7mil)MIN IMUN DESIRABLE TEST PAD POSITIONONG.035”(0.83MM)11.所有导通孔及气孔必须请PCB厂做MASK以防测试时漏气12.定位孔之定位针之尺寸误差在+-.002IN13.定位孔直径大于0.012IN14.定位孔之内壁不可吃锡15.治具之定位孔要用CNC钻孔*測試零件CHIP,CONNECT

4、OR為設計重點 *16.测试点不可被被绿漆盖住(测试前用放大镜检查)17.板边至测试点约0.125IN 不可有测试点.HOLE 18.测试点直径不小于0.35/0.50 in(35mil)，(目前约30mil)Solder pad(.09mm).035SOLDER RESISTPROBE TIP 19.导通孔之中心间距要150 mil 以上 20.各测试点必须吃锡，但边缘不可被绿漆MASK 21.如考虑功能测试时，要在CONNECTOR最进处加测试点 22.VCC点至少5点，GND点至少10点 以上为治具部份 23.对IC或CHIP之控制地址线(如RESET，ENABLE)不可直接接到VCC或

5、GROUND上4.7KNE OR CL 24.测试荡器须先除频或加JUMPER控制10pf VCC 25.对POWER- ON RESET在设计，要有隔离之设计4.7KRESET0.1UFVCCVCC414.7KOUT23OSCRESET 26.对振荡器如有控制ENABLE.DISABLE之产品测试会更稳，否则须加除频电路或善用JUMP亦是一 个好方法 27.对IC或CHIP之OPTION空脚要LAYOUT测试点 28.BGA零件背面之PCB不可LAYOUT零件 元件值ICT 短路 開路-IC Boundary Socan-IC PatternICT IC 元件功能自動調整ATE 組裝板功能測

6、試測試設備的功能及區隔 IC 保護二極體 靜態測試動態測試 -ICT：In-Circuit Tester-ATE：Automatic Test Equipment -MDA：Manufactureing Defect Analyzer 测试步骤完 成動 態靜 態產 品 自動調整 組裝板功能測試- IC Boundary Scan- IC Pattern IC保護二極體 IC元件功能 元件值 短路 開路制造不良分布高中低空板不良元件反插元件不良功能不良漏件/錯件短路/開路測試成本不良百分比高中低空板不良元件反插元件不良功能不良漏件/錯件短路/開路制造不良分布及测试成本 OKANON TR-518

7、 TESCON50K 美金以上 IC保護二極體 元件值 短路 開路50K 美金以上 TR-518F 自動調整 組裝板功能 HP TERADYNE-Boundart Scan-Pattern100K 美金以上 GenRad IC元件能價格產品測試功能测试设备的市场测试治具 In-Line測試治具 壓合式測試治具 真空測試治具 雙面測試治具 單面測試治具 加裝”導板”(Guiding Plate) 正確選擇測試點 正確選擇測試針頭 高品質的測試針治具制作的考虑因素SMT 制造不良问题未来趋势開路短路漏件/錯件功能不良元件不良元件反插高中低低IC PatternIC保護二極體元件值短路組裝板功能中開

8、路高SMT产品测试未来趋势AOI EQUIPMENT(AUTO OPTICAL INSPECTION) Performance standards in SMmanpowerinspection Drive to reducemonitoring and Focus on processSchedule demandsQuality and Lncreased cost,Electrical in inspectionProcessshipmentassembly orSystem Manufacturing keep risi Single-side SMT assembly process

9、 and finer pitch packag Lncreasing board dens access harder to attailmake in-circuit fixture Requirement to inspeccontrolcoverage inspectiontestable electricallydefect classes not5500-Series AOI systems from Teradyne provide process monitoring at any process stepSMT board assemblyLntegration/BoardEl

10、ectricalThru-Pick/ScreenWavePackagingTestFunctionalTestProcessloadholeReflowPlacePrintPre-wave inspection 5515B system Bottm-side solder joint quality Component insertion Solder joint quality,including J-leads and lifted leadsSingle-side SMT assembly process Component orientation Component presence

11、and alignment 5529 systemPost placement inspection The typical post-reflow SMT process Defect spectrum AOI and ICT are often employed together as Complementary tools ICTAOI Misoriented device(cap,TombstonedLifte leadsUnwetted pins Device progranmming (flashMissing devicesdevicesMissing bypass capsSk

12、ewed / misplacedLow solder ROM)Misoriented ICsBillboarded devicesDevices (still connected) diode)Device defects (e.g.cracked,ICWrong devicesShortsConnector pinspinsOpen power or parallel Basic device functionBGA and other hidden pins +Dose not require a fixture Built boards+Easily used on partiallyP

13、ossibly board function+Tests component function,and+Direct soldering-process+Can test hidden features+Applies board powerfeedbackAOI and ICT are often emplpyed together as*不須測試治具*基本零件之功能裝置之零件*BGA零件及其它穩藏腳位*電氣功能測試(有LIBRARY)*製程不良之問題*錯件ICT*缺件*墓碑效應*零件翹腳*短路*LAYOUT設計不良*零件偏移*bypass電容*零件外觀異常*錫少&錫多AOI測試之問題：*不

14、須上電及測試針*靜態各種外觀材料AOI Complementary tools *須製作治具及加電源 *能夠測試基板內部及穩藏之問題*能測試零件之功能特性容易修改*試產機種或機種少量變更時 *迅速且即時的反應製程問題The 5539-Series five camera head desugn*Structured light reveals the contours of the objectLight intensityMeasuring averagelnspectionSolder jointGoodComponent body under inspection Vertical ca

15、meraLn the system：In the window area if theComera reads low light Top lightingSolder joint is good 5500-Series system architectureVGAHigh accuracy X-Y table (0.001”accuracy over 18” x 20” board area)3/4 HP DC motors(29 in./s max.table speed)WarpStrobeLaser*(0.6”,0.7” or 1.0” FOV)1 or 5 high-speed ca

16、merasLED structured lighting dome*Board under inspectionBoard stops*Patented technologyConveyors (SMEMA interface) Window types detection with subpizellizationLocates the bright spot within the window(peakSearch intensity across the windowMeasures the averagePresence /Absence Average Presence /Absen

17、ce VarianceMeasures the average intensity across the window 100% Variance 0% Variance Looks for a continuous brigh strip across theBridge Window,either vertically or horizontally The defect detection capability requiredOutline IC SOICPassives(0603,0402)J-lead device Depends on the device packaging e

18、mployed BoardComprehensive visual or AOI solder jointInspection requires viewing from an angle Partial coveragedefect Full defect1.J-lead device coverage 2.Lifted lead on a QFPThe 5539 D+AOI (automated optical inspection) Systems from Teradyne5539 D+theory of operationLmage of a circuit board Comple

19、x image to process Hard to extract the key dataWindow approach Structured lighting highlights defects Apply simple criteria at critical points Automatically simplifies thr analysis Fast reliablerequiredInspection expamples using different combinationsof window types and lightingLighting from aboveSe

20、arch windowComponent locationLighting behind the cameraBridge windowsSolder short inspection(圖二)Side lighting.(“Snake eyes”) Solder joint inspectionPresence windows measuring variance(圖一)Lighting behind the cameraPresence windowComponent presence inspection An example of using structured light to in

21、spect for(圖三)about the solder joints Difficult to make a judgement Used for defecting solder bridgesTop lighting Solder joint defects defected(圖一)(圖二) Low variance in the window Bad jointsSide lighting High variance in the window Good jointsSide lighting defects on fine-pitch QFP Warp compensation B

22、oard warpage causes the image to move in the field of view of an angled camers The built-in warp measurement system measures the warp and automatically compensates for it during inspectionWarpage measurement technigue*Board warpage by looking at2.the cameras measure thethe position of the lineacross

23、 the board surfaceshines a bright line1.angled strobed laser warpagethe measurement of the boardstrobed on as required to freezeboard surface with the linecamera/lighting head over the3.the XY table moves the Programming an AOI system1.CAD output for pick and place2.Creat program usingpackage style,

24、orientation)systems(X,Y,designator,CDES (PC windows 3.1)and program stabilityverify defect coverage4.Performance CurvesComponents)100% missingreflowed board (i.e.Unpopulated,printed, Performance Curves are a key tool for guaranteeingprogram stability and defect coveragethe target inspection type(e.g

25、 for all 0603 passives)1.lnspect a known good board and save the measurement readings for2.lnspect a known bad(e.g the board with 100% low solder)andsave the measurement readings for the taret inspection type.3.Plot a histogram of the good and bad readings：set automatically5.lf this is not the case,

26、the programmer can refine the inspection(perhaps by modifying the lighting)to produce a more stable inspection.4.lf the two curves are separated,and the pass level is between the twocurves,then the system will reliably pass good boards and fail bad boards 6.Once the library is refined this step is not always required. CDES library for a 64 pin QFPCDES Library Designer-DEMO.LEG File Edit View Download Window Help 50X15-155.0BirdgeLG