EDA测试序列检测器.docx

1、EDA测试序列检测器EDA实验报告实验目的：设计一个含数码管显示的七位二进制序列发生器。实验内容：1.原理说明：多位数码显示电路由显示字符的段选线和选通数码管的位选线控制。各位数码管共用8位段选线的电路结构使得同一时刻选通的各位数码管显示相同字符。通过采用动态扫描显示方式，利用人眼视觉暂留效应及数码管余辉特性，可以“同时”显示出多位数码管的字符。2.工程结构框架：移位寄存器(序列发生器)7SEG译码器控制a b c d e f g 七段实验流程：1设计移位寄存器2设计7SEG译码器3完成顶层电路图连接,构成完整序列发生器4完成仿真，下载测试实验具体步骤：1、设计移位寄存器（序列发生器）序列发生

2、器是产生一组0、1二进制码按特定顺序排列的串行信号的仪器。利用移位寄存器设计一个七位二进制序列发生器。创建工程文件：单击界面左上角的file，执行file-New Project Wizard 命令，打开工程导向，在第一页中分别输入新建工程所在路径，工程名称和顶层实体名称（同名）器件选择：如上图，在Family中选择MAXII，如需修改可以选择菜单Assignments-Device命令，弹出Device设置对话框修改Device family和Available devices选项。创建设计文件： 利用lpm定制移位寄存器，在对话框左侧列表中选择Installed Plug-InsStora

3、gelpm_shiftreg项在参数设置中，设置移位方向为左移，数据并入并出端和串入串出端，异步清零。定制完成后生成的VHDL程序：- megafunction wizard: %LPM_SHIFTREG%- GENERATION: STANDARD- VERSION: WM1.0- MODULE: lpm_shiftreg - =- File Name: xulie.vhd- Megafunction Name(s):- lpm_shiftreg- Simulation Library Files(s):- lpm- =- *- THIS IS A WIZARD-GENERATED FILE

4、. DO NOT EDIT THIS FILE!- 9.0 Build 184 04/29/2009 SP 1 SJ Web Edition- *-Copyright (C) 1991-2009 Altera Corporation-Your use of Altera Corporations design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(in

5、cluding device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -

6、without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details.LIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY lpm;USE lpm.all;ENTITY xul

7、ie IS PORT ( aclr : IN STD_LOGIC ; clock : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (6 DOWNTO 0); load : IN STD_LOGIC ; shiftin : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); shiftout : OUT STD_LOGIC );END xulie;ARCHITECTURE SYN OF xulie IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (6 DOWNTO 0);

8、 SIGNAL sub_wire1 : STD_LOGIC ; COMPONENT lpm_shiftreg GENERIC ( lpm_direction : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( load : IN STD_LOGIC ; aclr : IN STD_LOGIC ; clock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); data : IN STD_LOGIC_VECTOR (6 DOWNTO 0); shiftout : OUT

9、STD_LOGIC ; shiftin : IN STD_LOGIC ); END COMPONENT;BEGIN q = sub_wire0(6 DOWNTO 0); shiftout RIGHT, lpm_type = LPM_SHIFTREG, lpm_width = 7 ) PORT MAP ( load = load, aclr = aclr, clock = clock, data = data, shiftin = shiftin, q = sub_wire0, shiftout = sub_wire1 );END SYN;- =- CNX file retrieval info

10、- =- Retrieval info: PRIVATE: ACLR NUMERIC 1- Retrieval info: PRIVATE: ALOAD NUMERIC 0- Retrieval info: PRIVATE: ASET NUMERIC 0- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC 1- Retrieval info: PRIVATE: CLK_EN NUMERIC 0- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING FLEX10K- Retrieval info: PR

11、IVATE: LeftShift NUMERIC 0- Retrieval info: PRIVATE: ParallelDataInput NUMERIC 1- Retrieval info: PRIVATE: Q_OUT NUMERIC 1- Retrieval info: PRIVATE: SCLR NUMERIC 0- Retrieval info: PRIVATE: SLOAD NUMERIC 1- Retrieval info: PRIVATE: SSET NUMERIC 0- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC 1- Retrie

12、val info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING 0- Retrieval info: PRIVATE: SerialShiftInput NUMERIC 1- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC 1- Retrieval info: PRIVATE: nBit NUMERIC 7- Retrieval info: CONSTANT: LPM_DIRECTION STRING RIGHT- Retrieval info: CONSTANT: LPM_TYPE STRING L

13、PM_SHIFTREG- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC 7- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock- Retrieval info: USED_PORT: data 0 0 7 0 INPUT NODEFVAL data6.0- Retrieval info: USED_PORT: load 0 0 0 0 INPUT NODEFV

14、AL load- Retrieval info: USED_PORT: q 0 0 7 0 OUTPUT NODEFVAL q6.0- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout- Retrieval info: CONNECT: clock 0 0 0 0 clock 0 0 0 0- Retrieval info: CONNECT: q 0 0 7 0 q 0 0

15、7 0- Retrieval info: CONNECT: shiftin 0 0 0 0 shiftin 0 0 0 0- Retrieval info: CONNECT: shiftout 0 0 0 0 shiftout 0 0 0 0- Retrieval info: CONNECT: load 0 0 0 0 load 0 0 0 0- Retrieval info: CONNECT: aclr 0 0 0 0 aclr 0 0 0 0- Retrieval info: CONNECT: data 0 0 7 0 data 0 0 7 0- Retrieval info: LIBRA

16、RY: lpm lpm.lpm_components.all- Retrieval info: GEN_FILE: TYPE_NORMAL xulie.vhd TRUE- Retrieval info: GEN_FILE: TYPE_NORMAL xulie.inc FALSE- Retrieval info: GEN_FILE: TYPE_NORMAL xulie.cmp TRUE- Retrieval info: GEN_FILE: TYPE_NORMAL xulie.bsf TRUE- Retrieval info: GEN_FILE: TYPE_NORMAL xulie_inst.vh

17、d FALSE- Retrieval info: LIB_FILE: lpm2、设计7SEG译码器7seg译码器VHDL程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity seg_7 isport( scan_clk,cnt_aclr:in std_logic; z0,z1,z2,z3,z4,z5,z6:in std_logic; seg7:out std_logic_vector(6 downto 0); wei:out std_logic_vector(6 downto 0);e

18、nd seg_7;architecture rtl of seg_7 issignal seg_wire:std_logic;signal wei_wire:std_logic_vector(6 downto 0);type st is (k_0,k_1,k_2,k_3,k_4,k_5,k_6);signal st_nxt:st; begin scan_st:process(scan_clk,cnt_aclr,st_nxt) begin if cnt_aclr=1 then st_nxt st_nxt st_nxt st_nxt st_nxt st_nxt st_nxt st_nxt seg_

19、wire=z0; wei_wire seg_wire=z1; wei_wire seg_wire=z2; wei_wire seg_wire=z3; wei_wire seg_wire=z4; wei_wire seg_wire=z5; wei_wire seg_wire=z6; wei_wire=1000000; end case; end process;seg7=1111110 when seg_wire=0 else 0110000 when seg_wire=1; weiCreate/updateCreate Symbol File for Current File命令并连接完成顶层

20、电路图：各模块功能说明：设定发生序列，发生序列设为1010101；利用LPM定制的移位寄存器，完成序列发生功能，利用shiftout端发生内定序列1010101。当移位寄存器并行输出端全为零时，重新载入序列10101017段译码器，完成数码管显示功能。4.功能仿真：在simulator settings中选择功能仿真功能仿真波形图：放大版：如上所示，scan_clk为七段译码器的时钟信号，在时钟上升沿时改变选通数码管的位选线，seg7为该数码管的位选线，因scan_clk时钟信号频率较高，利用人眼视觉暂留效应及数码管余辉特性，可以“同时”显示出多位数码管的字符。缩小版：如上图所示，clock为移位寄存器的数据串出端，在时钟上升沿改变向外输出，发射序列为1010101。5.管脚分配及下载