1、EDA程序改错题程序改错题1.已知sel为STD_LOGIC_VECTOR(1DOWNTO0)类型的信号,而a、b、c、d、q均为STD_LOGIC类型的信号,请判断下面给出的CASE语句程序片段: CASEselIS WHEN“00”=qqqq=d; ENDCASE; 答案:CASE语句缺“WHENOTHERS”语句。2.已知data_in1,data_in2为STD_LOGIC_VECTOR(15DOWNTO0)类型的输入端口,data_out为STD_LOGIC_VECTOR(15DOWNTO0)类型的输出端口,add_sub为STD_LOGIC类型的输入端口,请判断下面给出的程序片段:
2、 LIBRARYIEEE; USEIEEE.STD_LOGIC_1164.ALL; ENTITYaddIS PORT(data_in1,data_in2:ININTEGER; data_out:OUTINTEGER); ENDadd; ARCHTECTUREadd_archOFaddIS CONSTANTa:INTEGER=2; BEGIN data_out=(data_in1+data_in2)*a; ENDaddsub_arch;答案:常量声明时赋初值的“=”符号应改用“:=”符号。3.已知Q为STD_LOGIC类型的输出端口,请判断下面的程序片段: ARCHITECTUREtest_ar
3、chOFtestIS BEGIN SIGNALB:STD_LOGIC; QQQQQ=0;ENDCASE;ENDtest;【参考答案】:CASE语句应该存在于进程PROCESS内。2已知start为STD_LOGIC类型的信号,sum是INTEGER类型的信号,请判断下面的程序片断:PROCESS(start)BEGINFORiIN1TO9LOOPsum:=sum+i;ENDLOOP;ENDPROCESS;【参考答案】:sum是信号,其赋值符号应该由“:=”改为“=”。3已知Q为STD_LOGIC类型的输出端口,请判断下面的程序片断:ARCHITECTUREtestOFtestISBEGINSI
4、GNALB:STD_LOGIC;Q=B;ENDtest;【参考答案】:信号SIGNAL的申明语句应该放在BEGIN语句之前。4已知A和B均为STD_LOGIC类型的信号,请判断下面的语句:A=0;B=x;【参考答案】:不定态符号应该由小写的x改为大写的X。5已知A为INTEGER类型的信号,B为STD_LOGIC类型的信号,请判断下面的程序片断:ARCHITECTUREtestOFtestISBEGINBqqqq=d;ENDCASE;【参考答案】:CASE语句缺“WHENOTHERS”语句。四、判断下面程序中是否有错误,若有错误请改正;1、SIGNALA,EN:STD_LOGIC;PROCES
5、S(A,EN)VARIABLEB:STD_LOGIC;BEGINIFEN=1THENB=A;END;ENDPROCESS;2、 RCHITECTUREONEOFSAMPLEISVARIABLEA,B,C:INTEGER;BEGINC=A+B;END;五、判断下列程序是否有错误,如有则指出错误所在(10分)程序:LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYzyt12ISPORT(R,EN,CP:INbit;Q:BUFFERSTD_LO
6、GIC_VECTOR(0DOWNTO3);CO:OUTSTD_LOGIC);ENDzyt;ARCHITECTUREc10OFzyt12BEGINCO=1WHEN(EN=1ANDQ=1011)ELSE;0;PROCESS(R,CP)BEGINIFR=1THENQ=0000;ELSIF(CPEVENTANDCP=1)THENIFEN=0THENQ=Q;ELSIFQ=1011THENQ=0000;ELSEQ:=Q+1;ENDIF;ENDPROCESS;ENDone;仔细阅读下列程序,回答问题LIBRARYIEEE; -1USEIEEE.STD_LOGIC_1164.ALL; -2ENTITYLED7
7、SEGIS -3PORT( A :INSTD_LOGIC_VECTOR(3DOWNTO0); -4 CLK :INSTD_LOGIC; -5 LED7S:OUTSTD_LOGIC_VECTOR(6DOWNTO0); -6ENDLED7SEG; -7ARCHITECTUREoneOFLED7SEGIS -8 SIGNALTMP:STD_LOGIC; -9BEGIN -10 SYNC:PROCESS(CLK,A) -11 BEGIN -12 IFCLKEVENTANDCLK=1THEN -13 TMPLED7SLED7SLED7SLED7SLED7SLED7SLED7SLED7SLED7SLED7
8、SLED7S=00000001、LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCNT4BISPORT(CLK,RST,ENA:INSTD_LOGIC;OUTY:OUTSTD_LOGIC_VECTOR(3DOWNTO0);COUT:OUTSTD_LOGIC);ENDCNT4B;ARCHITECTUREbehavOFCNT4BISSIGNALCQI:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(CLK,RST,ENA)BEGINIFRST=1THENCQI=0
9、000;0000ELSIFCLKEVENTANDCLK=1THENIFENA=1THENCQI=CQI+1;1ELSECQI=0000;ENDIF;ENDIF;OUTY=CQI;ENDPROCESS;COUT=CQI(0)ANDCQI(1)ANDCQI(2)ANDCQI(3);ENDbehav;2、LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCLK_6DISPORT(CLK,RST:INSTD_LOGIC;CLK_OUT:OUTST
10、D_LOGIC);ENDCLK_6D;ARCHITECTUREONEOFCLK_6DISVARIABLETEMP:STD_LOGIC;SIGNALBEGINPROCESS(CLK)VARIABLECNT6D:INTEGERRANGE0TO3;CONSTANTSIGN:INTEGER:=2;BEGINIF(RST=“1”)THENTEMP=“0”;1,0ELSIFCLKEVENTANDCLK=1THEN(CLKEVENTANDCLK=1)IF(CNT6D=SIGN)THENCNT6D:=0;TEMP=NOTTEMP;ELSECNT6D:=CNT6D+1;ENDIF;ENDIF;ENDPROCES
11、S;CLK_OUTynull;endcase;endprocess;endone;4、LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcounterISPORT(reset:INSTD_LOGIC;clock:INSTD_LOGIC;num:bufferintegerrange0to3;多一个“;”);END;ARCHITECTUREbehavOFjishuISjishu改为counterBeginProcess(reset,clock)BeginIfreset=1thennum=0;Elsifrising_edge(clock)thenIfnum=3
12、thennum=0;elsenum=num+1;少endif;endif;endprocess;end;5、LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED;STD_LOGIC_UNSIGNED.ALLENTITYLX3_2ISPORT(CLK,CLR,OE:INBIT;D:INSTD_LOGIC_VECTOR(7DOWNTO0);Q:OUTSTD_LOGIC_VECTOR(7DOWNTO0);ENDLX3_2;ARCHITECTUREstrucOFLX3_2ISVARIABLEQ_TEMP:STD_LOGIC_
13、VECTOR(7DOWNTO0);SIGNALBEGINPROCESS(CLR)PROCESS(CLK)BEGINIFCLR=0THENQ_TEMP=00000000;00000000ELSIFCLK=1THENQ_TEMP=D;ELSEQ_TEMP=Q_TEMP;ENDIF;ENDPROCESS;Q=Q_TEMPWHENOE=1ELSEZZZZZZZZ;ENDstruc;6、LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYLX3_2ISPORT(A:INSTD_LOGIC_VECTOR(3DOWNTO0);B:INSTD_LOGIC(3DOWNTO0);STD_LOGIC_VECTORGT,LT,EQ:OUTSTD_LOGIC);ENDLX3_2;ARCHITECTUREoneOFLX8_2ISLX3_2BEGINPROCESS(A,B)BEGINGT=0;LT=0;EQBTHENGT=”0”;0ELSIFABTHENLT=”0”;0ELSEEQnull;附:自动化123江西理工大学王显聪
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