低功耗26万色TFT液晶单芯片驱动器集成电路毕业论文外文翻译Word文档格式.docx

1、AbstractIn this study, we present a 260 k-color TFT LCD one-chip driving IC that consumes under 5 mW in the module, which is exceptionally low power consumption. To reduce power consumption, we used many power-lowering schemes in the logic and analog design. A driver IC for driving LCDs has a built-

2、in graphic SRAM. Besides write and read operations, the graphic SRAM has a scan operation that is similar to the read operation of one row-line, which is displayed on one line in an LCD panel. Currently, the embedded graphic memory is implemented by an 8-transistor leaf cell and a 6-transistor leaf

3、cell. We propose an efficient scan method for a 6-transistor embedded graphic memory that is greatly improved over previous methods. The IC is implemented in a 0.18 um process. The 0.18um mixed process is firstly used in world.1.IntroductionCurrent telecommunication technology has improved amazingly

4、. These improvements have revitalized hand-held modules and increased services. Because of this, it is even more important that the chip enable voice communication, data, graphic images, and moving pictures. To use a hand-held module for a longer time, each chip needs to become smaller and consume l

5、ess power.Improvements in telecommunications have made display technology improve too. The size of display equipment has become bigger and the resolution higher. Due to this, power consumption of display equipment has also become higher. Power reduction for display equipment has become a very import

6、ant issue. The display equipment in hand-held phones is super twisted nematic （STN） and thin film transistor （TFT） LCDs. Electro-luminescence will be a practical utility. Display material can have an altered arrangement according to the level of voltage or the amount of current. In accordance with t

7、he arrangement, the rate of a transmission changes. We can control the brightness of a display panel, and the black/white display panel is implemented with this method. The multi-color display panel is implemented by arranging an RGB（red, green and blue） color filter. The color rectangular panel is

8、supplied by row-direct voltage and column-direct. voltage. The difference of the two direct voltages is the driving voltage of the pixels. This method is called multiplex addressing. The LCD driver IC generates and supplies the voltage level. This paper presents a 260 k-color TFT LCD one-chip driver

9、 module that consists of a gate driver and source driver. The gate driver generates the driving voltage of column direction and common voltage. Figure 1 shows how the TFT array is constructed. The gate driving voltage is of two types: a selected level and a non-selected level. The level of these vol

10、tages is determined by the characteristics of each panel. When one gate line is selected, the source IC drives data voltage levels that are valued by decoding stored data. The different voltage of the gates selected level and sources data level determine the display material arrangement.Currently, W

11、ith a higher color resolution, the embedded memory capacity needs to be bigger in the LCD driver IC. With a larger memory capacity, the metal line from the logic part to the memory needs to be longer. Because of this, the embedded graphic memory-addressing block, the embedded graphic memory control

12、block in the logic, and a time control block in the embedded graphic memory becomes more important in designing the embedded graphic memory. The internal control block in the embedded graphic memory is especially important in AC characterization. The power consumption of the merged memory also becom

13、es a very important issue. With a higher resolution and bigger panel, a bigger embedded memory size is necessary. Because of this, shrinking the RAM size is a dominant factor in the chip size of a driver IC. Because of these factors, the architecture of the embedded memory was improved from a 8-tran

14、sistor SRAM architecture to a 6-transistor SRAM architecture.In this paper, section II presents the architecture of graphic driving IC. Section III discusses the architecture of the 8-transistor/6-transitor embedded graphic SRAM and the architectural defect of the write/read/scan method in 6-transis

15、tor architecture. In section IV, a low power scan method in 6-transistor architecture is proposed. In this chapter, another low power accessed method is proposed. In Chapter V, the implemented sample is compared in power consumption. The chip samples are implemented in a 0.18 um process and tested i

16、n manual board.Figure. 1 TFT one-chip driver IC diagram2. Structure of the driver ICGenerally, the driver IC is composed of a logic part, an analog part, and a memory part. The analog part is composed of the LCD driver, DCDC converter, voltage divider, and oscillator. The oscillator circuit generate

17、s a clock for display. The DCDC converter circuit receives the generated clock and generates the highest/lowest voltage level. The voltage divider circuit divides between the highest and lowest level. The driver block supplies the various voltages to the panel. Figure 1 is a block diagram of the imp

18、lemented 260k TFT one-chip IC. The 260k TFT one-chip IC is composed of a logic, a merged memory, an oscillator, a DCDC converter block, a source/gate driver block and a common voltage generating block. The logic part is composed of an MPU interface block, memory-addressing block, and timing control

19、block. The MPU interface block interfaces between the driver IC and the external MPU. The memory-addressing block receives the decoded signal in the MPU interface and generates the memory address. The esister array is included in the gray scale generator. The implemented driving IC has three types o

20、f adjustment: a gradient adjustment, an amplitude adjustment, and a fine adjustment. The timing control block generates a signal, which controls the display panel. The gate driver block drives the gate on/off level voltage （VGH/VGOF）. The each voltage generating block sequencely generates each volta

21、ge. （Fig.2）. The TFT panel must have a capacitor for storage. The driving method is a two-type per capacitor connection that is named the capacitor for storage in a TFT panel （CST） on the gate and the CST on the common.The embedded memory is the same as normal memory. In addition, the embedded memor

22、y has the operation of accessing whole-bit cells in the X-address. The output data from memory is transferred to the source driver. The source driver drives the panel with the voltage level, which is decoded by the accessed data. One time, the gate driver circuit selects one line of the panel. The n

23、ext time, the gate driver circuit selects the next line, and the embedded memory transmits a whole-bit cell in the next X-address. The gate driver circuit selects a next-column line. With this accessing process, one line of the LCD panel is displayed.Figure. 2. Sequence of the voltage generatorFigur

24、e. 3. The proposed chip module3. Structure of graphic memoryThe embedded graphic SRAM is composed of a bit cell core block, I/O & pre-charge block, a control block, a scan line decoding block, a word-line decoding block, a scan latch block, and several buffer blocks. The bit core block stores displa

25、y data. The I/O & pre-charge block controls charging and discharging of the bit/bitb line. The scan/word line-decoding block controls the word-line cell in the bit core block. This block accesses stored data and stores data. The scan-latch block does scan operations.The control block receives extern

26、al write/read/scan enable signals from the address-generating block of the logic part and regenerates ram internal signals. The received-origin signal is transferred through a long metal line and the length of the metal line differs. Because of this, the write-enable signal of the most left word-lin

27、e block can have a time gap with the most right word-line block. The slope of the external signal through the long metal line is low and the driven gate of the sloped signal consumes more power. If the origin signal is used without refining the I/O block and word-line block, the operation of the mem

28、ory is unstable. Because of this instability, as the higher storage memory is embedded, regenerating the timing becomes more important.The regenerated signal enables the access operation when the bit/bitb line is perfectly stable. The control block has an auto-detect circuit, which detects the bit/b

29、itb stable time. In the 8-transistor graphic SRAM architecture, the read/write operation is the same as in a normal SRAM. However, a leaf cell has two additional transistors, which directly connect to the storage path. Because the additional two transistors are connected to the storage cell independ

30、ently of the bit/bitb line, the 2-transistor can independently access stored data.The additional transistor with a different access path makes it possible to access storage data even though write/read is operating. Because the 8-transistor has an independent scan operation, the memory access logic f

31、or the embedded graphic SRAM is simple. However, because of the additional 2-transistor, the chip size is bigger than the 6-transistor graphic SRAM. In a mono STN driver IC and a low-resolution multi-color STN driver, the embedded graphic SRAM size is not dominant in a full chip. As the panel become

32、s bigger and the resolution becomes higher, the size of the embedded graphic SRAM becomes dominant in the driver IC. Due to this, currently, the 6-transistor embedded graphic SRAM is used in 256/65 k/260 k color driver ICs. Figure 4. Comparison of 8-tr scan and 6-tr scan.In a 6-transistor graphic SRAM, the additional 2-transistor is removed. The scan operation is the same as in the read operation, but the select leaf cell is a whole column line of one row. Because the scan operation of the 6-transistor graphic SRAM uses a bit/bitb line, when the write