计算机组成原理实验参考答案(西南交大).docx

1、原创西南交通大学计算机组成实验参考答案注1、引脚分配依照EP3C40F780C8芯片注2、一定要参照实验指导书阅读此文实验一：多路数据选择器的设计f=(sel)a)+(sel)b)当sel=0时，f=a，否则f=b。引脚分配参考：a3:0 AH12 AF14 AA8 AB8b3:0 AF12 AG12 AA10 U8f3:0 E24 F22 E22 F21sel: AC5实验二 基于原理图方式的3-8译码电路的设计f0=(en)+(a)(b)(c)f1=(en)+(a)(b)cf2=(en)+(a)b(c)f3=(en)+(a)bcf4=(en)+a(b)(c)f5=(en)+a(b)cf6=

2、(en)+ab(c)f7=(en)+abcen为使能端，低电平有效，高电平时输出全为1。引脚分配参考：a: AH12，b: AF14，c: AA8，en: AC5f7:0 F24 H24 H23 L23 L24 M24 J22 AE8实验三 四位加法器设计实验思路：用Verilog HDL语言编写一位全加器，再用原理图方式用四个全加器组合实现四位加法器。Adder.vmodule Adder(a, b, cin, cout, sum); input a, b, cin; output cout, sum; assign cout, sum=a+b+cin; endmodule原理图：cout,

3、 sum=a+b+cincin为进位输入，cout为进位输出。引脚分配参考：a3:0 AH12 AF14 AA8 AB8b3:0 AF12 AG12 AA10 U8sum3:0 E24 F22 E22 F21cin: AC5，cout: F24实验四：七段LED数码管显示译码器设计本实验使用Verilog HDL实现。module Exp4(f, clk, rst, in, out, sel); input 15:0in; /输入 input f, clk, rst; /计数开关，时钟，置零开关 output reg7:0out; /数码管输出 output reg2:0sel; /数码管3-

4、8译码器输出 reg15:0counter; reg3:0data; reg clk_alt; reg9:0l; /change frequency变频段 always (posedge clk) begin if(l=1023)l=0; else l=l+1; clk_alt=l2; end /select 选择在哪一个数码管显示 always (posedge clk) begin sel=sel+1; if(sel=4)sel=0; case(sel) 0:data=counter3:0; 1:data=counter7:4; 2:data=counter11:8; 3:data=cou

5、nter15:12; endcase end /count and reset 计数和清零 always (posedge clk_alt or posedge rst) begin if (rst=1) counter=0; else if (f=1) counter=in; else counter=counter+1; end /translate 译码段，此处可以使用二进制或十六进制，后面的实验同，不再赘述。 always case(data) 0:out=63; 1:out=6; 2:out=91; 3:out=79; 4:out=102; 5:out=109; 6:out=125;

6、 7:out=7; 8:out=127; 9:out=111; 10:out=119; 11:out=124; 12:out=57; 13:out=94; 14:out=121; 15:out=113; endcase endmodule引脚分配参考：in15:0 AH12 AF14 AA8 AB8 AF12 AG12 AA10 U8 AF5 AH6 AH7 AH8 AH14 AG7 AG8 AF9out7:0 M21 G12 G14 G15 G18 F18 G17 G16sel2:0 G9 D22 C22clk: A14，f: AC5，rst: AD4实验五：算数逻辑单元（ALU）设计mod

7、ule Exp5(s, cin, d, wt, sel, out, slt, clk); input 2:0s; /功能开关 input sel, cin, wt, clk; /选择输入开关，进位输入，写入开关，时钟 input 15:0d; /输入 output reg 7:0out; /数码管输出 output reg 2:0slt; /数码管3-8译码器输出 reg 15:0a; /暂存器a reg 15:0b; /暂存器b reg 15:0result; /计算结果 reg 3:0outdata; reg cout;/选择显示的数码管always (posedge clk) begin

8、 slt=slt+1; if(slt=5)slt=0; case(slt) 0:outdata=cout; 1:outdata=result15:12; 2:outdata=result11:8; 3:outdata=result7:4; 4:outdata=result3:0; endcase end/译码always case(outdata) 0:out=63; 1:out=6; 2:out=91; 3:out=79; 4:out=102; 5:out=109; 6:out=125; 7:out=7; 8:out=127; 9:out=111; 10:out=119; 11:out=12

9、4; 12:out=57; 13:out=94; 14:out=121; 15:out=113; endcase /选择输入到哪一个暂存 always (sel or wt) begin if(wt=0) begin if(sel=0)a=d; else b=d; end end /计算功能选择 always case(s) 0: result=0; /置零 1: result=a&b; /逻辑与 2: result=a|b; /逻辑或 3: result=ab; /逻辑异或 4: cout, result=a+b+cin; /算术加 5: cout, result=a1; /a右移一位 7:

10、 ; /无功能 endcase endmodule引脚分配参考：d15:0 AH12 AF14 AA8 AB8 AF12 AG12 AA10 U8 AF5 AH6 AH7 AH8 AH14 AG7 AG8 AF9out7:0 M21 G12 G14 G15 G18 F18 G17 G16slt2:0 G9 D22 C22s2:0 AE4 AC5 AD4clk: A14，cin: AH11，sel: AE3，wt: AH10实验六 CPU寄存器组的设计module Exp6(RA, wt, rd, m, rst, clk, d, out, sel); input 1:0RA; /通用寄存器选择

11、input rd, wt, rst, clk; /读开关，写开关，置零开关，时钟 input 1:0m; /功能选择 input 15:0d; /输入 output reg 7:0out; /数码管输出 output reg 2:0sel; /数码管3-8译码器输出 reg 3:0data; reg 15:0R0; reg 15:0R1; reg 15:0R2; reg 15:0R3; reg 15:0mid; reg 15:0counter; reg clk_alt; reg 2:0l; /变频段 always (negedge clk) begin if(l=7)l=0; else l=l

12、+1; clk_alt=l2; end /读写 always (RA or rd or wt) begin case(RA) 0:begin if(rd=1 & wt=0)R0=d; else if(rd=0 & wt=1)mid=R0; end 1:begin if(rd=1 & wt=0)R1=d; else if(rd=0 & wt=1)mid=R1; end 2:begin if(rd=1 & wt=0)R2=d; else if(rd=0 & wt=1)mid=R2; end 3:begin if(rd=1 & wt=0)R3=d; else if(rd=0 & wt=1)mid=R

13、3; end endcase end /PC寄存器 always (negedge clk_alt) begin if(rst=0)counter=0; else case(m) 0:; /无功能 1:counter=counter-1; /减一计数 2:counter=counter+1; /加一计数 3:counter=mid; /置数 endcase end /输出 always (negedge clk) begin sel=sel+1; if(sel=8)sel=0; case(sel) 0:data=counter15:12; 1:data=counter11:8; 2:data=

14、counter7:4; 3:data=counter3:0; /前四位显示PC寄存器数值 4:data=mid15:12; 5:data=mid11:8; 6:data=mid7:4; 7:data=mid3:0; /后四位显示通用寄存器数值 endcase end /译码always case(data) 0:out=63; 1:out=6; 2:out=91; 3:out=79; 4:out=102; 5:out=109; 6:out=125; 7:out=7; 8:out=127; 9:out=111; 10:out=119; 11:out=124; 12:out=57; 13:out=

15、94; 14:out=121; 15:out=113; endcase endmodule引脚分配参考：RA1:0 AG10 AG11，m1:0 AE4 AC5d15:0 AH12 AF14 AA8 AB8 AF12 AG12 AA10 U8 AF5 AH6 AH7 AH8 AH14 AG7 AG8 AF9out7:0 M21 G12 G14 G15 G18 F18 G17 G16sel2:0 G9 D22 C22clk: A14，rst: AH11，rd: AE3，wt: AD4实验七 运算器设计此实验用Verilog HDL和原理图实现ALU.v ALU部分（功能参照实验五）module

16、ALU(s, cin, wt, sel, in, cout, out); input 2:0s; input sel, cin, wt; input 15:0in; output reg 15:0out; output reg cout; reg 15:0a; reg 15:0b; always (sel or wt) begin if(wt=0) begin if(sel=0)a=in; else b=in; end end always case(s) 0: out=0; 1: out=a&b; 2: out=a|b; 3: out=ab; 4: cout, out=a+b+cin; 5:

17、 cout, out=a2; 7: ; endcase endmoduleREG.v CPU寄存器组部分（功能参照实验六）module REG(in, out, slt, d, RA, wr, m, rst, clk, sel, mid); input 15:0in; input 15:0d; input 1:0RA; input wr, rst, clk, sel; /sel为选择开关，选择从ALU的输出出入或者外部输入 input 1:0m; output reg7:0out; output reg2:0slt; reg 3:0data; reg 15:0R0; reg 15:0R1; r

18、eg 15:0R2; reg 15:0R3; output reg 15:0mid; reg 15:0counter; reg clk_alt, wt, rd; reg 2:0l; always (negedge clk) begin if(l=7)l=0; else l=l+1; clk_alt=l2; end /Read and Write always begin case(RA) 0:begin if(wr=0) if(sel=1)R0=d; else R0=in;/sel高电平从外部输入，否则从ALU输入，下同 else mid=R0; end 1:begin if(wr=0) if

19、(sel=1)R1=d; else R1=in; else mid=R1; end 2:begin if(wr=0) if(sel=1)R2=d; else R2=in; else mid=R2; end 3:begin if(wr=0) if(sel=1)R3=d; else R3=in; else mid=R3; end endcase end /PC always (negedge clk_alt) begin if(rst=0)counter=0; else case(m) 0:; 1:counter=counter-1; 2:counter=counter+1; 3:counter=

20、d; endcase end /output always (negedge clk) begin slt=slt+1; if(slt=8)slt=0; case(slt) 0:data=counter15:12; 1:data=counter11:8; 2:data=counter7:4; 3:data=counter3:0; 4:data=mid15:12; 5:data=mid11:8; 6:data=mid7:4; 7:data=mid3:0; endcase end /translate always case(data) 0:out=63; 1:out=6; 2:out=91; 3

21、:out=79; 4:out=102; 5:out=109; 6:out=125; 7:out=7; 8:out=127; 9:out=111; 10:out=119; 11:out=124; 12:out=57; 13:out=94; 14:out=121; 15:out=113; endcase endmodule两个文件写完之后分别生成symbol文件，并绘制原理图由于实验箱只有28个开关输入，因此为节省引脚，将cin接地或接+5V，并将实验六的读写开关合二为一。引脚分配参考：d15:0 AH12 AF14 AF12 AG12 AF5 AH6 AH7 AH8 AG10 AG11 AH14

22、 AG7 AG8 AF9 AH10 AH11out7:0 M21 G12 G14 G15 G18 F18 G17 G16slt2:0 G9 D22 C22，s2:0 AA8 AB8 AE4，m1:0 AE3 AD4，RA1:0 AA10 U8clk: A14，cout: AE8，rst: J27，sel_alu: AC5，sel_reg: J28，wr: Y28，wt_alu: Y27实验八 指令存储器与取指令部件的设计此实验用Verilog HDL和原理图实现PC.v 取地址部分module PC(pc_in, load, rst, clk_pc, add, out); input rst,

23、 clk_pc, add, load; /置零开关、时钟、加1控制输入、置数开关 input 7:0pc_in; output reg 7:0out;always (posedge clk_pc) begin if(rst=0)out=0; else if(load=0)out=pc_in; else if(add=1)out=out+1; /当加1控制有效时，地址加1 endendmoduleFRQ.v 分频部分module FRQ(clk_in, clk_out); input clk_in; output reg clk_out; reg 2:0l; always (posedge cl

24、k_in) begin l=l+1; clk_out=l2; /8分频 end endmoduleIR.v取指令部分module IR(in, add, wr, clk_ir, clk_scn, out, sel); input 15:0in; /地址输入 input wr, clk_ir, clk_scn; /显示开关，显示频率，刷新频率 output reg add; /加1控制（与PC相连） output reg7:0out; /数码管输出 output reg2:0sel; /数码管3-8译码器输出 reg 3:0data;always (posedge clk_scn) begin sel=sel+1; if(sel=4)sel=0; case(sel) 0:data=in15:12; 1:data=in11:8; 2:data=in7:4; 3:data=in3:0; endcase endalways (posedge clk_ir) begin if(wr=0)add=1; /每当显示1次，地址加1 else add=0;