东南大学CPU报告.docx

1、东南大学CPU报告Micro-programmed CPUReportCOA Course Design止于至善contentsPurpose .2Experiment Principle .2Instruction Set .2Internal Registers and Memory.3MAR (Memory Address Register).3 MBR (Memory Buffer Register).4 PC (Program Counter) .4IR (Instruction Register).4ACC (Accumulator) .5MR (Multiplier Regist

2、er).5 DR (Division Register) .5LPM_RAM_DQ.5 ALU (Arithmetic Logic Unit).6Micro-programmed Control Unit .6CPU Architecture .8Control signals in Control Memory .8Contents of Control Memory .9Top level circuit diagram .11Simulation results:.12Problem 1: Calculate the sum of all integers from 1 to 100.1

3、2Problem 2: Calculate 300 and 275 .14 Results Analysis .14Further Improvement .15Reference .15Appendix .151MBR module.15 2BR module .163ALU module .174IR module .18 5PC module .19 6MAR module.207control_unit module .21 8MR module.22 1止于至善PurposeThe purpose of this project is to design a simple CPU (

4、Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its performance. For simplicity, we will only consider the relationship among the CPU, registers, memory and instruction set. That is to say we only need

5、to consider the following items: Read/Write Registers, Read/Write Memory and execute the instructions.At least four parts constitute a simple CPU: the control unit, the internal registers, the ALU and instruction set, which are the main aspects of our project design and will be studied.Experiment Pr

6、incipleInstruction SetSingle-address instruction format is used in our simple CPU design. The instruction word contains two sections: the operation code (opcode), which defines the function of instructions (addition, subtraction, logic operations, etc.); the address part, in most instructions, the a

7、ddress part contains the memory location of the datum to be operated, we called it direct addressing. In some instructions, the address part is the operand, which is called immediate addressing.For simplicity, the size of memory is 25616 in the computer. The instruction word has 16 bits. The opcode

8、part has 8 bits and address part has 8 bits. The instruction word format can be expressed in Figure 1Figure 1 the instruction formatThe opcode of the relevant instructions are listed in Table 1. In Table 1, the notation x represents the contents of the location x in the memory. For example, the inst

9、ruction word 00000011101110012 (03B916) means that the CPU adds word at location B916 in memory into the accumulator (ACC); the instruction word 00000101000001112 (050716) means if the sign bit of the ACC (ACC 15) is 0, the2止于至善CPU will use the address part of the instruction as the address of next

10、instruction, if the sign bit is 1, the CPU will increase the program counter (PC) and use its contentInternal Registers and MemoryMAR (Memory Address Register)MAR contains the memory location of the word to be read from the memory or written into the memory. Here, READ operation is denoted as the CP

11、U reads from memory, and WRITE operation is denoted as the CPU writes to memory. In our design, MAR has 8 bits to access one of 256 addresses of the memory.In my experiment, the MAR block is as figure 2marinst6Figure 23止于至善MBR (Memory Buffer Register)MBR contains the value to be stored in memory or

12、the last value read from memory. MBR is connected to the address lines of the system bus. In our design, MBR has 16 bits.In my experiment, the MBR block is as figure 3mbrinst3Figure 3PC (Program Counter)PC keeps track of the instructions to be used in the program. In our design, PC has 8 bits.In my

13、experiment, the PC block is as figure 4Figure 4IR (Instruction Register)IR contains the opcode part of an instruction. In our design, IR has 8 bits. BR (Buffer Register) BR is used as an input of ALU, it holds other operand for ALU. In our design, BR has 16 bits.In my experiment, the Instruction reg

14、ister is as figure 54止于至善Figure 5ACC (Accumulator)ACC holds one operand for ALU, and generally ACC holds the calculation result of ALU. In our design, ACC has 16 bits.MR (Multiplier Register)MR is used for implementing the MPY instruction, holding the multiplier at the beginning of the instruction.

15、When the instruction is executed, it holds part of the product.In my experiment, the MR is as figure 6Figure 6DR (Division Register)DR is used for implementing the DIV instruction, you can define it according to your division algorithm. Its optional. Here, we ignore it.LPM_RAM_DQLPM_RAM_DQ is a RAM

16、with separate input and output ports, it works as memory, and its size is 25616. Although its not an internal register of CPU, we need it to simulate and test the performance of CPU. All the registers are positive-edge- triggered. All the reset signals for the registers are ALU .5止于至善Figure 7ALU (Ar

17、ithmetic Logic Unit)ALU is a calculation unit which accomplishes basic arithmetic and logic operations. In our design, some operations must be supported which are listed as follows e synchronized to the clock signal.In my experiment, the ALU block is as figure 8Figure 8Table 2 ALU operationsMicro-pr

18、ogrammed Control UnitWe have learnt the knowledge of Micro-programmed control unit. Here, we only review some terms and basic structures. In the Micro-programmed control, the micro-program consists of some microinstructions and the micro-program is stored in control memory that generates all the con

19、trol signals required to execute the6止于至善instruction set correctly. The microinstruction contains some micro-operations which are executed at the same time.Microinstructions are stored in the control memory. The control address register contains the address of the next microinstructions to be read.

20、When a microinstruction is read from the control memory, it is transferred to a control buffer register. The register connects to the control lines emanating from the control unit. Thus, reading a microinstruction from the control memory is the same as executing that microinstruction. The third elem

21、ent shown in the figure 9 is a sequencing unit that loads the control address register and issues a read command.Control MemoryControl Buffer RegisterFigure 9 Control UnitIn my CPU, the control address is defined as a variable, without a single part. The control unit is as figure 10.And the control

22、memory is as figure 11.7止于至善control_unitinst2Figure 10lpm_rom0inst8Figure 11CPU ArchitectureFigure 12Control signals in Control MemoryTable 3 Control Signals8止于至善Bit in read-onlycontrol memory(Bit of ROM)Micro-operationControl signal nameC0CARCAR+1Increase CARC1CAR*Control addressingC2CAR0Reset CARC3MBRmemoryRead RAMC4IRopcodeMBR(15.8)MBR into IRopcodeC5MARMBR7.0MBR into MARC6PCPC+1Increase PCC7BRMBRMBR into BRC8ACC0reset_ACCC9ACCACC+BRAD