硬件描述语言范例.docx

1、硬件描述语言范例硬件描述语言语言设计实例1、8-3编码器module encode_verilog ( a ,b );input 7:0 a ; /编码器输入wire 7:0 a ;output 2:0 b ; /编码器输出reg 2:0 b; always ( a ) begin case ( a ) /编码器某一输入端口为高电平输出相应的3位二进制数 8b0000_0001 : b=3b000; /0 8b0000_0010 : b=3b001; /1 8b0000_0100 : b=3b010; /2 8b0000_1000 : b=3b011; /3 8b0001_0000 : b=3

2、b100; /4 8b0010_0000 : b=3b101; /5 8b0100_0000 : b=3b110; /6 8b1000_0000 : b=3b111; /7 default : b= 3b000; /其他情况编码器输出3b000 endcase endendmodule2、8-3优先编码器module p_encode_verilog ( A ,I ,GS ,EO ,EI ); /编码器以低为有效input 7:0 I ; /编码器输入wire 7:0 I ;input EI ; /输入使能，EI=0时，编码器正常工作wire EI ; output 2:0 A ; /编码器输

3、出reg 2:0 A ; output GS ; /优先编码器工作状态标志，编码器的八个输入端有信号输入时，GS=0 reg GS ; output EO ; /输出使能，reg EO ; always ( I or EI ) if ( EI ) /使用if、else if表明条件的优先级顺序 begin A = 3b111; GS = 1; EO = 1; end else if ( I7 = 0 ) begin A = 3b000; GS = 0; EO = 1; end else if ( I6 = 0 ) begin A = 3b001; GS = 0; EO = 1; end els

4、e if ( I5 = 0 ) begin A = 3b010; GS = 0; EO = 1; end else if ( I4 = 0 ) begin A = 3b011; GS = 0; EO = 1; end else if ( I3 = 0 ) begin A = 3b100; GS = 0; EO = 1; end else if ( I2 = 0 ) begin A = 3b101; GS = 0; EO = 1; end else if ( I1 = 0 ) begin A = 3b110; GS = 0; EO = 1; end else if ( I0 = 0 ) begi

5、n A = 3b111; GS = 0; EO = 1; end else if ( I = 8b11111111) begin A = 3b111; GS = 1; EO = 0; endendmodule3、3-8译码器module decoder_verilog ( G1 ,Y ,G2 ,A ,G3 ); input G1 ; /使能输入，高有效wire G1 ;input G2 ; /使能输入，低有效wire G2 ;input 2:0 A ; /3位译码器输入，为高有效wire 2:0 A ; input G3 ; /使能输入wire G3 ; /使能输入，低有效output 7:0

6、 Y ; /8位译码器输出，为低有效reg 7:0 Y ;reg s;always ( A ,G1, G2, G3) begin s = G2 | G3 ; if ( G1 = 0) /G1为低有效 Y = 8b1111_1111; else if ( s) Y = 8b1111_1111; else case ( A )3b000 : Y= 8b1111_1110; 3b001 : Y= 8b1111_1101; 3b010 : Y= 8b1111_1011; 3b011 : Y= 8b1111_0111; 3b100 : Y= 8b1110_1111; 3b101 : Y= 8b1101_

7、1111; 3b110 : Y= 8b1011_1111; 3b111 : Y= 8b0111_1111; endcase endendmodule4、数据选择器module mux8_1_verilog ( Y ,A ,D0, D1, D2, D3, D4, D5, D6, D7 ,G );input 2:0 A ; /地址输入端wire 2:0 A ;input D0 ; /数据输入端input D1 ; /数据输入端input D2 ; /数据输入端input D3 ; /数据输入端input D4 ; /数据输入端input D5 ; /数据输入端input D6 ; /数据输入端in

8、put D7 ; /数据输入端input G ; /使能端，当G=1时Y=0，当G=0时数据选择器正常工作wire G ;output Y ; /数据输出端reg Y ;always (G or A or D0 or D1 or D2 or D3 or D4 or D5 or D6 or D7 ) begin if (G = 1) /使能端的优先级高 Y B ) Y B时Y输出3b001 else if ( A = B) Y = 3b010; /A = B时Y输出3b010 else Y = 3b100; /A B时Y输出3b100 endendmodule6、全加器module sum_ve

9、rilog ( A ,Co ,B ,S ,Ci );input A ; /输入加数Awire A ;input B ; /输入加数Bwire B ;input Ci ; /相邻低位的进位输入信号wire Ci ;output Co ; /向相邻高位的进位输出信号reg Co ;output S ; /相加和数输出reg S ;always ( A or B or Ci) begin if ( A= 0 & B = 0 & Ci = 0 ) begin S = 0; Co = 0; end else if ( A= 1 & B = 0 & Ci = 0 ) begin S = 1; Co = 0

10、; end else if ( A= 0 & B = 1 & Ci = 0 ) begin S = 1; Co = 0; end else if ( A=1 & B = 1 & Ci = 0 ) begin S = 0; Co = 1; end else if ( A= 0 & B = 0 & Ci = 1 ) begin S = 1; Co = 0; end else if ( A= 1 & B = 0 & Ci = 1 ) begin S = 0; Co = 1; end else if ( A= 0 & B = 1 & Ci = 1 ) begin S = 0; Co = 1; end

11、else begin S = 1; Co = 1; end end endmodule7、D触发器module Dflipflop ( Q ,CLK ,RESET ,SET ,D ,Qn );input CLK ; /D触发器输入时钟wire CLK ;input RESET ; /D触发器清零输入wire RESET ;input SET ; /D触发器预置数输入wire SET ;input D ; /D触发器输入wire D ;output Q ; /D触发器输出reg Q ;output Qn ; wire Qn ;assign Qn = Q ; /将D触发器输出取反always (

12、posedge CLK or negedge SET or negedge RESET ) begin if ( !RESET) /RESET下降沿将D触发器输出清零 Q = 0 ; else if ( ! SET) /SER下降沿将D触发器输出置1 Q = 1; else Q = D; /CLK上升沿D触发器输出等于输入 endendmodule8、寄存器module reg8 ( clr ,clk ,DOUT ,D );input clr ; /异步清零信号，高有效wire clr ;input clk ; /时钟输入wire clk ;input 7:0 D ; /寄存器数据输入wire

13、 7:0 D ;output 7:0 DOUT ; /寄存器数据输出reg 7:0 DOUT ;always ( posedge clk or posedge clr) begin if ( clr = 1b1) DOUT = 0; else DOUT = D ; endendmodule9、双向移位寄存器module shiftdata ( left_right ,load ,clr ,clk ,DIN ,DOUT );input left_right ; / 左移右移控制信号wire left_right ;input load ; /异步置数信号，有效时将DIN输入wire load ;

14、input clr ; /异步清零信号，高有效wire clr ;input clk ; /时钟输入wire clk ;input 3:0 DIN ; /并行输入wire 3:0 DIN ;output 3:0 DOUT ; /并行输出wire 3:0 DOUT ; / DOUT是一个wire型变量，不能在always块中被赋值 reg 3:0 data_r; /所以定义一个寄存器型变量data_r作为中间变量assign DOUT = data_r ;always ( posedge clk or posedge clr or posedge load ) begin if ( clr =

15、1) /异步清零 data_r = 0; else if (load ) /异步置数 data_r = DIN; else begin if ( left_right) /left_right=1，信号左移 begin data_r = (data_r1); data_r0 = 0; /移出位补0 end else begin /left_right=0，信号右移 data_r 1); data_r3 = 0; /移出位补0 end end endendmodule10、4位二进制加减法计数器module counter4 ( load ,clr ,c ,DOUT ,clk, up_down

16、,DIN);input load ; /异步预置数input clk; /输入时钟wire load ;input clr ; /异步清零wire clr ;input up_down ; /加减计数，up_dpwn=1加计数，up_down=0减计数wire up_down ;input 3:0 DIN ; /预置数输入wire 3:0 DIN ;output c ; /进位/借位输出，可以用于计数器的级联reg c ;output 3:0 DOUT ; /计数输出wire 3:0 DOUT ;reg 3:0 data_r;assign DOUT = data_r;always ( pose

17、dge clk or posedge clr or posedge load)begin if ( clr = 1) /异步清零 data_r = 0; else if ( load = 1) /异步预置 data_r = DIN; else begin if ( up_down =1) /加计数 begin if ( data_r = 4b1111) begin data_r = 4b0000; c = 1; end else begin data_r = data_r +1; c = 0 ; end end else /减计数 begin if ( data_r = 4b0000) beg

18、in data_r = 4b1111; c = 1; end else begin data_r = data_r -1; c = 0 ; end end end end endmodule11、十进制加减法计数器module counter10 ( load ,clr ,c ,DOUT ,clk, up_down ,DIN ,seven_seg);input load ; /异步预置数input clk; /输入时钟wire load ;input clr ; /异步清零wire clr ;input up_down ; /加减计数，up_dpwn=1加计数，up_down=0减计数wire

19、 up_down ;input 3:0 DIN ; /预置数输入wire 3:0 DIN ;output c ; /进位/借位输出，可以用于计数器的级联reg c ;output 3:0 DOUT ; /计数输出output 7:0 seven_seg; /7段数码管wire 3:0 DOUT ;reg 3:0 data_r;assign DOUT = data_r;always ( posedge clk or posedge clr or posedge load)begin if ( clr = 1) /异步清零 data_r = 0; else if ( load = 1) /异步预置

20、 data_r = DIN; else if ( up_down =1 & data_r = 9) /加进位 begin c = 1; data_r = 4b0000; end else if ( up_down =0 & data_r = 0) /减借位 begin c = 1; data_r = 9; end else begin if (up_down =1) begin /加计数 data_r = data_r +1; c = 0 ; end else begin /减计数 data_r = data_r -1 ; c = 0 ; end end end /*数码管*/ assign

21、seven_seg =Y_r; reg 7:0 Y_r;always (data_r ) /用7段数码管显示计数输出beginY_r =8b11111111; case (data_r ) 4b0000: Y_r = 8b00000011; /显示0 4b0001: Y_r = 8b10011111; /显示14b0010: Y_r = 8b00100101; /显示24b0011: Y_r = 8b00001101; /显示34b0100: Y_r = 8b10011001; /显示44b0101: Y_r = 8b01001001; /显示54b0110: Y_r = 8b01000001

22、; /显示64b0111: Y_r = 8b00011111; /显示74b1000: Y_r = 8b00000001; /显示84b1001: Y_r = 8b00001001; /显示9default: Y_r = 8b11111111; /默认数码管不发光 endcaseend endmodule12、顺序脉冲发生器module pulsegen ( Q ,clr ,clk);input clr ; /异步预置数wire clr ;input clk ; /时钟输入wire clk ;output 7:0 Q ;/顺序脉冲输出wire 7:0 Q ;reg 7:0 temp ;reg

23、x;assign Q =temp;always ( posedge clk or posedge clr )begin if ( clr=1) begin temp = 8b00000001; /temp寄存预定的序列 x= 0 ; end else begin x= temp7 ; /序列最高位输出 temp = temp1 ; /temp左移一位 temp0 =x; /将输出的结果赋给序列最低位，实现序列的循环输出 end end endmodule13、序列信号发生器module xlgen ( Q ,clk ,res);input clk ; /时钟输入wire clk ;input

24、res ; /异步预置数wire res ;output Q ; /序列信号输出reg Q ;reg 7:0 Q_r ;always ( posedge clk or posedge res) begin if (res =1) begin Q = 1b0; Q_r = 8b11100100 ;/Q_r寄存预定的序列 end else begin Q = Q_r7; /序列最高位输出 Q_r = Q_r1; /Q_r左移一位 Q_r0 =Q; /将输出的结果赋给序列最低位，实现序列的循环输出 end endendmodule14、分频器module clockdiv ( Q ,rst ,sys

25、clk ,sel );input rst ; /系统复位wire rst ;input sysclk ; /系统时钟输入wire sysclk ;input 1:0 sel ; /分频倍数选择wire 1:0 sel ;output Q ; /分频器输出wire Q ;reg 2:0 q;reg 31:0 cnt ;reg clk ; /时钟分频模块always ( posedge sysclk or negedge rst) begin if ( !rst ) begin cnt = 0 ; clk = 1b1 ; end else begin cnt = 32d2500000 ) begin /clk时钟周期是系统时钟周期的