16位模型机的设计.docx

1、16位模型机的设计16位CPU的设计要求：此模型机的功能是将存储区的数据块复制到另一个存储区。汇编代码如下： START： LOADI R1，0010H ;源操作数地址送R1LOADI R2，0030H ；目的操作数地址送R2LOADI R6，002FH ；结束地址送R6NEXT： LOAD R3，R1 ；取数STORE R2，R3 ；存数BRANCHGTI START ；如果R1R6，则转向STARTINC R1 ；修改源地址INC R2 ；修改目的地址BRANCHI NEXT ；转向NEXT1. 16位CPU的组成结构2. 指令系统的设计一、 指令格式1) 单字指令格式2) 双字指令格式二

2、、 指令操作码操作码指令功能00001LOAD装载数据到寄存器00010STORE将寄存器的数据存入到存储器00100LOADI将立即数装入到寄存器00101BRANCHI无条件转移到由立即数指定的地址00110BRANCHGTI如果源寄存器容大于目的寄存器的容，则转移到由立即数指定的地址00111INC寄存器容加1指令依据以上设计的指令系统，则完成数据块复制的程序如下：地址机器码指令 功能说明0000H0001H2001H0010HLOADI R1，0010H源操作数地址送R10002H0003H2002H0030HLOADI R2，0030H目的操作数地址送R20004H0005H2006

3、H002FHLOADI R6，002FH结束地址送R60006H080BHLOAD R3，R1取数0007H101AHSTORE R2，R3存数0008H 0009H300EH0000HBRANCHGTI 0000如果R1大于R6，则转向地址0000000AH3801HINC R1修改源地址000BH3802HINC R2修改目的地址000CH000DH2800H0006HBRANCHI 0006H转向00006H，实现循环3. VHDL设计一、 程序包：说明运算器的功能、移动寄存器的操作、比较器的比较类型和用于CPU控制的状态类型。library ieee;use ieee.std_logi

4、c_1164.all;use ieee.std_logic_arith.all;package cpu_lib is subtype t_shift is unsigned (3 downto 0);constant shftpass :unsigned(3 downto 0):=0000;constant sftl :unsigned(3 downto 0):=0001;constant sftr:unsigned(3 downto 0):=0010;constant rotl :unsigned(3 downto 0):=0011;constant rotr :unsigned(3 dow

5、nto 0):=0100;subtype t_alu is unsigned(3 downto 0);constant alupass :unsigned(3 downto 0):=0000;constant andOp :unsigned(3 downto 0):=0001;constant orOp:unsigned(3 downto 0):=0010;constant notOp :unsigned(3 downto 0):=0011;constant xorOp :unsigned(3 downto 0):=0100;constant plus :unsigned(3 downto 0

6、):=0101;constant alusub :unsigned(3 downto 0):=0110;constant inc :unsigned(3 downto 0):=0111;constant dec :unsigned(3 downto 0):=1000;constant zero:unsigned(3 downto 0):=1001;subtype t_comp is unsigned 2 downto 0);constant eq :unsigned(2 downto 0):=000;constant neq :unsigned(2 downto 0):=001;constan

7、t gt:unsigned(2 downto 0):=;constant gte :unsigned(2 downto 0):=011;constant lt :unsigned(2 downto 0):=100;constant lte :unsigned(2 downto 0):=101;subtype t_reg is std_logic_vector(2 downto 0);type state is (reset1,reset2,reset3,reset4,reset5,reset6,execute,nop,load,store,move,load2,load3,load4,stor

8、e2,store3,store4,move2,move3,move4,incPc,incPc2,incPc3,incPc4,incPc5,incPc6,loadPc,loadPc2,loadPc3,loadPc4,bgtI2,bgtI3,bgtI4,bgtI5,bgtI6,bgtI7,bgtI8,bgtI9,bgtI10,braI2,braI3,braI4,braI5,braI6,loadI2,loadI3,loadI4,loadI5,loadI6,inc2,inc3,inc4);subtype bit16 is std_logic_vector(15 downto 0);end cpu_li

9、b;二、基本部件的设计1) 运算器的设计 功能library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use work.cpu_lib.all;entity alu is port(a,b:in bit16;sel:in t_alu;c:out bit16);end alu;architecture rt1 of alu is begin process(a,b,sel)begincase sel iswhen alupass= c c c c c c c c c c c if a=b then comp

10、out =1 after 1ns; else compout if a/=b then compout =1 after 1ns; else compout if ab then compout =1 after 1ns; else compout if a=b then compout =1 after 1ns; else compout if ab then compout =1 after 1ns; else compout if a=b then compout =1 after 1ns; else compout compout y y y y y y=000000000000000

11、0 after 1 ns;end case;end process;end rt1;4) 寄存器library ieee;use ieee.std_logic_1164.all;use work.cpu_lib.all;entity reg is port(a:in bit16;clk:in std_logic;q:out bit16);end reg;architecture rt1 of reg isbeginprocessbeginwait until clkevent and clk=1;q=a after 1ns;end process;end rt1;5) 寄存器组library

12、ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use work.cpu_lib.all;entity regarray is port(data:in bit16;sel:in t_reg;en,clk:in std_logic;q:out bit16);end regarray;architecture rt1 of regarray is type t_ram is array (0 to 7) of bit16;signal temp_data:bit16;beginprocess(clk,sel) va

13、riable ramdata:t_ram;begin if clkevent and clk=1 then ramdata(conv_integer(sel):=data; end if; temp_data=ramdata(conv_integer(sel) after 1 ns;end process;process(en,temp_data)begin if en=1 then q=temp_data after 1 ns; else q=ZZZZZZZZZZZZZZZZ after 1 ns; end if;end process;end rt1;6) 三态寄存器library iee

14、e;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use work.cpu_lib.all;entity trireg isport(a:in bit16;en,clk:in std_logic;q:out bit16);end trireg;architecture rt1 of trireg issignal val:bit16;beginprocess begin wait until clkevent and clk=1; val=a; end process;process(en,val)begin if en

15、=1 then q=val after 1 ns; elsif en=0 then q=ZZZZZZZZZZZZZZZZ after 1 ns; else q=XXXXXXXXXXXXXXXX after 1 ns; end if;end process;end rt1;7) 控制器采用状态机实现library IEEE;use IEEE.std_logic_1164.all;use work.cpu_lib.all;entity control is port( clock,reset,compout:in std_logic; instrReg:in bit16; progCntrWr,p

16、rogCntrRd,addrRegWr,outRegWr,outRegRd:out std_logic; shiftSel:out t_shift; aluSel:out t_alu; compSel:out t_comp; opRegRd,opRegWr,instrWr,regRd,regWr,rw,vma:out std_logic; regSel:out t_reg );end control;architecture rtl of control is signal current_state, next_state : state; begin process( current_st

17、ate, instrReg, compout) begin progCntrWr = 0; progCntrRd = 0; addrRegWr = 0; outRegWr = 0;outRegRd = 0; shiftSel = shftpass; aluSel = alupass; compSel = eq;opRegRd = 0; opRegWr = 0; instrWr = 0; regSel = 000;regRd = 0; regWr = 0; rw = 0; vma aluSel=zero after 1 ns; shiftSel=shftpass; next_state aluS

18、el=zero; shiftSel=shftpass; outRegWr=1; next_state outRegRd=1; next_state outRegRd=1; progCntrWr=1;addrRegWr=1; next_state vma=1; rw = 0; next_state vma=1; rw=0;instrWr=1; next_state case instrReg(15 downto 11) is when 00000 = next_state regSel=instrReg(5 downto 3); regRd=1;next_state regSel=instrRe

19、g(2 downto 0); regRd=1;next_state regSel=instrReg(5 downto 3); regRd=1; aluSel=alupass;shiftSel=shftpass; next_state progcntrRd=1; alusel=inc; shiftsel=shftpass;next_state progcntrRd=1; alusel=inc; shiftsel=shftpass;next_state regSel=instrReg(5 downto 3); regRd=1;next_state regSel=instrReg(2 downto

20、0); regRd=1; alusel=inc;shiftsel=shftpass; next_statenext_state regSel = instrReg(5 downto 3); regRd = 1;addrregWr = 1; next_state vma = 1; rw = 0; next_state vma = 1; rw = 0; regSel = instrReg(2 downto 0);regWr = 1; next_state regSel = instrReg(2 downto 0); regRd = 1;addrregWr = 1; next_state regSe

21、l = instrReg(5 downto 3); regRd = 1;next_state regSel = instrReg(5 downto 3); regRd = 1; rw = 1; next_state regSel = instrReg(5 downto 3); regRd = 1;aluSel =alupass;shiftsel = shftpass; outRegWr = 1; next_state outRegRd = 1; next_state outRegRd = 1;regSel = instrReg(2 downto 0); regWr = 1; next_stat

22、e progcntrRd = 1; alusel = inc; shiftsel = shftpass;outregWr = 1; next_state outregRd = 1; next_state outregRd = 1; progcntrWr=1; addrregWr=1;next_state vma = 1; rw = 0; next_state vma = 1; rw = 0;regSel = instrReg(2 downto 0);regWr = 1; next_state progcntrRd = 1; alusel = inc; shiftsel = shftpass;outregWr = 1; next_state outregRd = 1; next_state = braI4;wh