vhdl设计中地常见错误.docx

1、vhdl设计中地常见错误一Vhdl语言中1提示：VHDL syntax error:expected choice in case statementCase 语句中没覆盖到所有的情况，要加 when others=null;=二在verge hdl语句中在QuartusII下进展编译和仿真的时候,会出现一堆warning,有的可以忽略,有的却需要注意,虽然按F1可以了解关于该警告的帮助,但有时候帮助解释的仍然不清楚,大家群策群力,把自己知道和了解的一些关于警告的问题都说出来讨论一下,免得后来的人走弯路.下面是我收集整理的一些,有些是自己的经验,有些是网友的,希望能给大家一点帮助,如有不对的地

2、方,请指正,如果觉得好,请版主给点威望吧,谢谢1.Found clock-sensitive change during active clock edge at time on register 原因：vector source file中时钟敏感信号如：数据，允许端，清零，同步加载等在时钟的边缘同时变化。而时钟敏感信号是不能在时钟边沿变化的。其后果为导致结果不正确。措施：编辑vector source file2.Verilog HDL assignment warning at : truncated value with size to match size of target (原因

3、:在HDL设计中对目标的位数进展了设定,如:reg4:0 a;而默认为32位,将位数裁定到适宜的大小措施:如果结果正确,无须加以修正,如果不想看到这个警告,可以改变设定的位数3.All reachable assignments to data_out(10) assign 0, register removed by optimization原因:经过综合器优化后，输出端口已经不起作用了4.Following 9 pins have nothing, GND, or VCC driving datain port - changes to this connectivity may chan

4、ge fitting results原因:第9脚，空或接地或接上了电源措施:有时候定义了输出端口，但输出端直接赋0，便会被接地，赋1接电源。如果你的设计中这些端口就是这样用的，那便可以不理会这些warning5.Found pins functioning as undefined clocks and/or memory enables原因:是你作为时钟的PIN没有约束信息。可以对相应的PIN做一下设定就行了。主要是指你的某些管脚在电路当中起到了时钟管脚的作用，比如flip-flop的clk管脚，而此管脚没有时钟约束，因此QuartusII把“clk作为未定义的时钟。措施:如果clk不是时钟

5、，可以加“not clock的约束；如果是，可以在clock setting当中参加；在某些对时钟要求不很高的情况下，可以忽略此警告或在这里修改:AssignmentsTiming analysis settings.Individual clocks. 注意在Applies to node中只用选择时钟引脚一项即可，required fmax一般比所要求频率高5%即可，无须太紧或太松。6.Timing characteristics of device EPM570T144C5 are preliminary原因:因为MAXII 是比較新的元件在 QuartusII 中的時序並不是正式版的,

6、要等 Service Pack措施:只影响 Quartus 的 Waveform7.Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled措施:将setting中的timing Requirements&Option-More Timing Setting-setting-Enable Clock Latency中的on改成OFF8.Found clock high time violation at 14.8 ns on reg

7、ister |counter|lpm_counter:count1_rtl_0|dffs11原因:违反了steup/hold时间，应该是后仿真，看看波形设置是否和时钟沿符合steup/hold时间措施:在中间加个存放器可能可以解决问题9.warning: circuit may not operate.detected 46 non-operational paths clocked by clock clk44 with clock skew larger than data delay原因:时钟抖动大于数据延时,当时钟很快，而if等类的层次过多就会出现这种问题,但这个问题多是在器件的最高频

8、率中才会出现措施：setting-timing Requirements&Options-Default required fmax 改小一些，如改到50MHZ10.Design contains input pin(s) that do not drive logic原因:输入引脚没有驱动逻辑(驱动其他引脚,所有的输入引脚需要有输入逻辑措施:如果这种情况是故意的,无须理会,如果非故意,输入逻辑驱动.11.Warning：Found clock high time violation at 8.9ns on node TEST3.CLK原因：FF中输入的PLS的保持时间过短措施：在FF中设置较

9、高的时钟频率12.Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks - node(s) analyzed as buffer(s) resulting in clock skew原因:如果你用的 CPLD 只有一组全局时钟时，用全局时钟分频产生的另一个时钟在布线中当作信号处理，不能保证低的时钟歪斜(SKEW)。会造成在这个时钟上工作的时序电路不可靠，甚至每次布线产生的问题都不一样。措施:如果用有两组以上全局时钟的芯片，可以把第二个全局时钟作为另一个时钟用，可以解决

10、这个问题。FPGA13.Critical Warning: Timing requirements were not met. See Report window for details.原因：时序要求未满足，措施：双击pilation Report-Time Analyzer-红色局部如clock setup:clk等-左键单击list path,查看fmax的SLACK REPORT再根据提示解决,有可能是程序的算法问题或fmax设置问题14.Warning: Cant find signal in vector source file for input pin |whole|clk10

11、m原因：这个时因为你的波形仿真文件 vector source file 中并没有把所有的输入信号(input pin)加进去，对于每一个输入都需要有激励源的15.Cant achieve minimum setup and hold requirement along path(s). See Report window for details.原因：时序分析发现一定数量的路径违背了最小的建立和保持时间，与时钟歪斜有关,一般是由于多时钟引起的措施：利用pilation Report-Time Analyzer-红色局部如clock hold:clk等，在slack中观察是hold time为

12、负值还是setup time 为负值，然后在：Assignment-Assignment Editor-To中增加时钟名(from node finder)，Assignment Name中增加和多时钟有关的Multicycle 和Multicycle Hold选项，如hold time为负，可使Multicycle hold的值multicycle,如设为2和1。16: Cant analyze file - file E:/quartusii/*/*.v is missing原因：试图编译一个不存在的文件，该文件可能被改名或者删除了措施：不管他，没什么影响17.Warning: Cant

13、find signal in vector source file for input pin |whole|clk10m原因：因为你的波形仿真文件 vector source file 中并没有把所有的输入信号(input pin)加进去，对于每一个输入都需要有激励源的18.Error: Cant name logic function scfifo0 of instance inst - function has same name as current design file原因：模块的名字和project的名字重名了措施：把两个名字之一改一下，一般改模块的名字19.Warning: U

14、sing design file lpm_fifo0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: lpm_fifo0原因：模块不是在本项目生成的，而是直接copy了别的项目的原理图和源程序而生成的，而不是用QUARTUS将文件添加进本项目措施：无须理会，不影响使用20.Timing characteristics of d

15、evice are preliminary原因：目前版本的QuartusII只对该器件提供初步的时序特征分析措施：如果坚持用目前的器件，无须理会该警告。关于进一步的时序特征分析会在后续版本的Quartus得到完善。21.Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family原因：用analyze_latches_as_synchronous_elements setting可以让Quaruts II来分析同步

16、锁存，但目前的器件不支持这个特性措施：无须理会。时序分析可能将锁存器分析成回路。但并不一定分析正确。其后果可能会导致显示提醒用户：改变设计来消除锁存器,但实际其实无关紧要22.Warning:Found xx output pins without output pin load capacitance assignment原因：没有给输出管教指定负载电容解决方法：该功能用于估算TCO和功耗，可以不理会，也可以在Assignment Editor中为相应的输出管脚指定负载电容，以消除警告1 Warning: VHDL Process Statement warning at random.vh

17、d(18): signal reset is in statement, but is not in sensitivity list-没把singal放到process中2 Warning: Found pins ing as undefined clocks and/or memory enablesInfo: Assuming node CLK is an undefined clock-=-可能是说设计中产生的触发器没有使能端3 Error: VHDL Interface Declaration error in clk_gen.vhd(29): interface object cl

18、k_scan of mode out cannot be read. Change object mode to buffer or inout.-信号类型设置不对，out当作buffer来定义4 Error: Node instance clk_gen1 instantiates undefined entity clk_gen-引用的例化元件未定义实体entity clk_gen5 Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks - node(s) analy

19、zed as buffer(s) resulting in clock skewInfo: Detected ripple clock clk_gen:clk_gen1|clk_incr as bufferInfo: Detected ripple clock clk_gen:clk_gen1|clk_scan as buffer6 Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable dataout may not be assigned a new in every possible pa

20、th through the Process Statement. Signal or variable dataout holds its previous in every path with no new assignment, which may create a binational loop in the current design.7 Warning: VHDL Process Statement warning at divider_10.vhd(17): signal t is read inside the Process Statement but isnt in th

21、e Process Statements sensivitity list -缺少敏感信号8 Warning: No clock transition on counter_bcd7:counter_counter_clk|q_sig3 register9 Warning: Reduced register counter_bcd7:counter_counter_clk|q_sig3 with stuck clock port to stuck GND10 Warning: Circuit may not operate. Detected 1 non-operational path(s)

22、 clocked by clock class1 with clock skew larger than data delay. See pilation Report for details.11 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock sign with clock skew larger than data delay. See pilation Report for details.12 Error: VHDL error at counter_clk.v

23、hd(90): actual port class of mode in cannot be associated with formal port class of mode out-两者不能连接起来13 Warning: Ignored node in vector source file. Cant find corresponding node name class_sig2 in design.-没有编写testbench文件，或者没有编辑输入变量的值 testbench里是元件申明和映射14 Error: VHDL Binding Indication error at freqd

24、etect_top.vhd(19): port class in design entity does not have std_logic_vector type that is specified for the same generic in the associated ponent-在相关的元件里没有当前文件所定义的类型15 Error: VHDL error at tongbu.vhd(16): cant infer register for signal gate because signal does not hold its outside clock edge16 Warn

25、ing: Found clock high time violation at 1000.0 ns on register |fcounter|lpm_counter:temp_rtl_0|dffs417 Warning: piler packed, optimized or synthesized away node temp19. Ignored vector source file node.-temp19被优化掉了18 Warning: Reduced register gatereg0 with stuck data_in port to stuck GND19 Warning: D

26、esign contains 2 input pin(s) that do not drive logicWarning: No output dependent on input pin clkWarning: No output dependent on input pin sign-输出信号与输入信号无关，20 Warning: Found clock high time violation at 16625.0 ns on register |impulp|gate121 Error: VHDL error at impulp.vhd(19): cant implement clock

27、 enable condition specified using binary operator or22 Error: VHDL Association List error at period_counter.vhd(38): actual parameter assigned to formal parameter alarm, but formal parameter is not declared-连接表错误，形参alarm赋值给实参，形参没定义，可能是形参与实参的位置颠倒了，规定形参在实参之前。23 Error: Ignored construct behavier at per

28、iod_counter.vhd(15) because of previous errors因为前一个错误而导致的错误24 Error: VHDL error at period_counter.vhd(38): type of identifier alarm does not agree with its usage as std_logic typealarm的定义类型与使用的类型不一致25 Error: VHDL error at shift_reg.vhd(24): cant synthesize logic for statement with conditions that te

29、st for the edges of multiple clocks-同一进程中含有两个或多个if(edge)条件，一个进程中之能有一个时钟沿26 Error: Cant resolve multiple constant drivers for net datain_reg22 at shift_reg.vhd(19)27 cant infer register for signal num0 because signal does not hold its outside clock edge28Error: Cant elaborate top-level user hierarchy

30、29 Error: Cant resolve multiple constant drivers for net cs_in at led_key.vhd(32) -有两个以上赋值语句，不能确定“cs_in的值，30 Warning: Ignored node in vector source file. Cant find corresponding node name over in design.-在源文件中找不到对应的节点“over。31 Error: Cant access JTAG chain无法找到下载链32 Info: Assuming node clk is an undefined clock1.Found clock-sensitive change during active clock edge at time on register 原因：vector source file中时钟敏感信号如：数据，允许端，清零，同步加载等在时钟的边缘同时变化。而时钟敏感信号是不能在时钟边沿变化的。其后果为导致结果不正确。措施：编辑vector source file2.Verilog HDL assignment warning at : truncated with size to match size of target