1、2、设计万年历的基本逻辑思路3、创建工程,创建新文件,编写万年历的程序4、编译程序,检查错误5、添加管脚约束6、波形仿真7、综合、实现、下载8、完成实验报告与总结四、实验原理万年历原理 秒、分是60进制,时是24进制,日31天由月1.3.5.7.8.10.12控制,日28/29由2月和润年控制,日30由月4.6.9.11控制。原理如下图: 图1万年历结构模块图五、VHDL程序1、主程序library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;use IEEE.std_logic_unsigned.all;entity m
2、ain is Port ( clk : in STD_LOGIC; light : out STD_LOGIC_VECTOR (7 downto 0); cpld_en : out STD_LOGIC_VECTOR (1 downto 0); led_en : out STD_LOGIC_VECTOR (7 downto 0);end main;architecture Behavioral of main is signal result: std_logic_vector(3 downto 0); signal clknew: std_logic; signal clknew_s: sig
3、nal flag:integer range 1 to 8; signal Counter: Integer RANGE 1 TO 50; signal fenpin28s: signal as: signal bs: signal couts: signal T1s: signal T2s: signal runs: signal N1s: signal N2s:signal y1s: signal y2s: signal cout1s: component clk_devider is Port ( clkin : clkout : out STD_LOGIC); end componen
4、t; component day IS PORT( fenpin28: in std_logic; a,b : T1,T2 : out std_logic_vector(3 downto 0); cout : out std_logic); component devider is port(clk:in std_logic; fenpin28:out std_logic); component led is Port ( key_in : in STD_LOGIC_VECTOR (3 downto 0); light_out : clk : in STD_LOGIC); component
5、nian IS PORT(COUT1:IN STD_LOGIC; N1,N2:OUT STD_LOGIC_VECTOR (3 DOWNTO 0); run:OUT STD_LOGIC); component yue IS PORT(cout,run: Y1,Y2: a,b:OUT STD_LOGIC; COUT1:begin cpld_en=01; u1:clk_devider port map (clk,clknew); u2:devider port map (clk,fenpin28s); u3:led port map (result,light,clknew_s); u4:day p
6、ort map(fenpin28s,as,bs,T1s,T2s,couts); u5:nian port map(COUT1s,N1s,N2s,runs); u6:yue port map(couts,runs,Y1s,Y2s,as,bs,COUT1s);process(clknew) BEGIN IF (clknewevent AND clknew =1) THEN IF Counter= 10 THEN Counter = 1; clknew_s=NOT clknew_s; ELSE Counterled_en01111111result0010flag101111110000 when
7、3 =11011111=N1s; when 4 =11101111=N2s; when 5 =11110111=Y1s; when 6 =11111011=Y2s; when 7 =11111101=T1s; when 8 =11111110=T2s; when others = flag=1; end case; else null; end if; end process;end Behavioral;2、分频模块(1)第一个分频模块use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the fo
8、llowing library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity clk_devider isend clk_devider;architecture Behavioral of clk_devider is Integer RANGE 1 TO 5000; SIGNAL Clk:std_logic;PROCESS(clkin) IF (clkinevent AND clkin = IF Count
9、er= 5000 THEN Clk=NOT Clk; clkout =Clk;(2)第二个分频模块ENTITY devider IS PORT( clk: END devider;ARCHITECTURE Behavioral OF devider IS SIGNAL temp:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL tmp: INTEGER RANGE 0 TO 49999999;SIGNAL clk_out: STD_LOGIC;BEGIN PROCESS(clk) IF clkevent AND clk= THEN IF tmp=49999999 THE
10、N tmp=0; ELSE=tmp+1; END IF; IF tmp=24999999 THEN clk_out=0END PROCESS ;fenpin28=clk_out;3、日模块ENTITY day ISEND day;Architecture Behavioral of day issignal ab: STD_LOGIC_VECTOR(1 DOWNTO 0);signal Q1,Q2: STD_LOGIC_VECTOR(3 DOWNTO 0);BeginPROCESS(fenpin28,a,b)ab=a&b;IF fenpin28EVENT AND fenpin28=IF Q1=
11、9 THEN Q1Q2=Q2+1;else Q1=Q1+1;end if;if ab=00 then if Q2=3 AND Q1=1 THEN Q2 Q10001 cout else cout end if;elsif ab=then if Q2=3 and Q1=0 THEN ;cout10 if Q2=2 AND Q1=8 then11 if Q2=2 AND Q1=9 thenelse null;END IF;T1=Q1;T2=Q2;END Behavioral;4、月模块ENTITY yue ISPORT(cout,run:END yue ;ARCHITECTURE Behavior
12、al OF yue ISsignal Q2,Q1:STD_LOGIC_VECTOR (3 DOWNTO 0);signal Q2Q1:STD_LOGIC_VECTOR (7 DOWNTO 0);SIGNAL a1,b1:STD_LOGIC;PROCESS(cout,run)IF coutEVENT AND cout= IF Q1=9 THEN IF Q2=1 AND Q1=2 THENCOUT1 ELSE COUT1end PROCESS;PROCESS(q2,q1)Q2Q1=Q2&Q1;IF Q2Q1=00000001 OR Q2Q1=0000001100000101000010000001
13、000000010010THEN a1b1ELSIF Q2Q1=00000010 THEN IF run= a1 else a1ELSE a1Y1Y2a=a1;b=b1;5、年模块ENTITY nian ISPORT(COUT1:END nian;ARCHITECTURE Behavioral OF nian ISsignal Q1,Q2,Q3:PROCESS(COUT1,Q1,Q2)IF COUT1EVENT AND COUT1= IF Q2=9 THEN ELSE Q3=Q3+1; IF Q3=3 THENrun ELSE runN1N2light_outZZZZZZZZ -when ot
14、hers =NULL; end if; end process;六、仿真波形图 图2 时钟分频模块仿真波形图图 图3 LED显示模块仿真波形图七、管脚约束管脚约束文件如下:八、心得体会万年历的大作业,让我从中收获很多,感触也很多。通过完成大作业,我对ISE又有了更深的理解。以前有很多不知道的东西,在完成作业的过程中大部分的问题都得到了解决。这次实训,我不仅仅在知识上得到很大程度的提升,对VHDL的编程操作更加熟悉,而且,分析问题和解决问题的能力得到很大的提升。最后,很感谢我的指导老师。感谢她对我的悉心指导,在遇到瓶颈,止步不前时能给我们指明方向,帮忙解决问题。谢谢老师!九、参考文献1肖特 著. VHDL大学实用教程 电子工业出版社 2010年2潘松 黄继业 著.EDA技术实用教程 科学出版社2010年3 张丕状 著.基于VHDL的CPLDFPGA开发与应用 电子工业出版社2009年 4 邢建平 著. VHDL程序设计高等学校教材 清华大学出版社2008年
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