veriloghdl电子琴课程设计.docx

1、veriloghdl电子琴课程设计veriloghdl电子琴课程设计 Verilog HDL electric piano module fractional frequency 第一章 系统设计 第一节 课题目标及总体方案 本次项目设计课程的目标是让我们在学习Verilog HDL的基础上更加深入的理解硬件设计语言的功能、作用及其特征，并且将我们的动手能力与创新能力结合起来。本次电子琴实验的目标是： 1、具有手动弹奏和自动播放功能； 2、以按键（或开关）作为琴键，至少可以通过蜂鸣器输出7个音阶； 3、自动播放曲目至少两首； 本次实验的方框图为：（每个模块中都有分频） 主模块 九个键 Key1

2、到Key7用于弹奏 Key8与Key9（mm）用于选择歌曲 mm=00 按键模块 Key1 到 Key7 模块名digital_piano mm=01 曲目1两只老虎 模块名 bell mm=10 曲目2康定情歌 模块名 bell2 mm=11 曲目3天空之城 模块名 bell3 第二节 设计框图说明 一、 主模块 主模块中用mm=(key8,key9)值的不同选择调用不同模块，mm=01调用曲目1模块，即bell模块； mm=10调用曲目2模块，即bell2模块； mm=11调用曲目3模块，即bell3模块； 而在key8与key9没有被按下的情况下，程序调用按键模块，即digital_pi

3、ano模块 module main(inclk,outclk,key1,key2,key3,key4,key5,key6,key7,key8,key9,num); input inclk; input key1,key2,key3,key4,key5,key6,key7,key8,key9; output outclk; output3:0num; reg outclk,clk_6M; reg 3:0c; wire out1,out2,out3,out4; wire8:0 key; reg 1:0mm; assign key = key1,key2,key3,key4,key5,key6,ke

4、y7,key8,key9; /由按键拼键为变量key /调用子调块 digital_piano m1(.inclk(inclk),.key1(key1),.key2(key2),.key3(key3),.key4(key4), .key5(key5),.key6(key6),.key7(key7),.beep2(out2),.num(num); bell m2(.inclk(inclk),.beep1(out1); bell2 m3(.inclk(inclk),.beep3(out3); bell3 m4(.inclk(inclk),.beep4(out4); always (posedge

5、clk_6M) /在时钟的上升沿检测是否有按键按下 begin if(key = 9b*-*0) mm = 2b01; else if(key=9b*-*1) mm = 2b10; else if(key=9b*-*0) mm = 2b11; else mm = 2b00; end always(posedge inclk) begin if(c4d4) c=c+4d1; else begin c=4d0; clk_6M=clk_6M; end end always (posedge clk_6M) begin if(mm = 2b01) outclk = out1; else if(mm =

6、 2b00) outclk = out2; else if(mm = 2b10) outclk = out3; else outclk = out4; end endmodule 二、按键模块 Key1到key7对应do到si七个音，用于模拟电子琴弹奏 /digital_piano子模块 module digital_piano(inclk,key1,key2,key3,key4,key5,key6,key7,beep2,num); input inclk,key1,key2,key3,key4,key5,key6,key7; output3:0num; output beep2; wire

7、6:0 key_code; reg 3:0c; reg clk_6M; reg beep_r; reg 3:0num; reg 15:0 count; reg 15:0 count_end; parameter Do = 7b*-*, /状态机的7个编码，分别对应中音的7个音符 re = 7b*-*, mi = 7b*-*, fa = 7b*-*, so = 7b*-*, la = 7b*-*, si = 7b*-*; assign key_code = key7,key6,key5,key4,key3,key2,key1; assign beep2 = beep_r; /输出音乐 alway

8、s(posedge inclk) begin if(c4d4) c=c+4d1; else begin c=4d0; clk_6M=clk_6M; end end always(posedge clk_6M) /分频模块，得出乐谱 begin count = count + 16d1; /计数器加1 if(count = count_end) begin count =16d0; /计数器清零 beep_r = !beep_r; end end always(posedge clk_6M) /状态机，根据按键状态，选择不同的音符输出 begin case(key_code) Do: count

9、_end = 16d*; re: count_end = 16d*; mi: count_end = 16d09090; fa: count_end = 16d08571; so: count_end = 16d07802; la: count_end = 16d06802; si: count_end = 16d06060; default:count_end = 16d0; endcase end always (posedge clk_6M) begin case(key_code) Do: num=4b0001; re: num=4b0010; mi: num=4b0011; fa:

10、num=4b0100; so: num=4b0101; la: num=4b0110; si: num=4b0111; endcase end endmodule 二、 曲目1模块 /bell子模块 两只老虎 module bell (inclk,beep1); input inclk; /系统时钟 output beep1; /蜂鸣器输出端 reg 3:0high,med,low; reg 15:0origin; reg beep_r; /寄存器 reg 7:0state; reg 15:0count; assign beep1=beep_r; /输出音乐 /时钟频率6MHz reg clk

11、_6MHz; reg 2:0 cnt1; always(posedge inclk) begin if(cnt13d4) cnt1=cnt1+3b1; else begin cnt1=3b0; clk_6MHz=clk_6MHz; end end /时钟频率4MHz reg clk_4Hz; reg 24:0 cnt2; always(posedge inclk) begin if(cnt225d*-*) cnt2=cnt2+25b1; else begin cnt2=25b0; clk_4Hz=clk_4Hz; end end always (posedge clk_6MHz) begin

12、count = count + 1b1; /计数器加1 if(count = origin) begin count = 16h0; /计数器清零 beep_r = !beep_r; /输出取反 end end always(posedge clk_4Hz) begin case(high,med,low) 12b*-*0000:origin=*;/mid1 12b*-*0000:origin=*;/mid2 12b*-*0000:origin=9101;/mid3 12b*-*0000:origin=8590;/mid4 12b*-*0000:origin=7653;/mid5 12b*-*

13、0000:origin=6818;/mid6 12b*-*0101:origin=*;/low5 endcase end always (posedge clk_4Hz) /歌曲 two tiger begin if(state =63) state = 0;/计时，以实现循环演奏 else state = state + 1; case(state) 0,1: high,med,low=12b*-*0000;/mid1 2,3: high,med,low=12b*-*0000;/mid2 4,5: high,med,low=12b*-*0000;/mid3 6,7: high,med,low

14、=12b*-*0000;/mid1 8,9: high,med,low=12b*-*0000;/mid1 10,11: high,med,low=12b*-*0000;/mid2 12,13: high,med,low=12b*-*0000;/mid3 14,15: high,med,low=12b*-*0000;/mid1 16,17: high,med,low=12b*-*0000;/mid3 18,19: high,med,low=12b*-*0000;/mid4 20,21,22,23: high,med,low=12b*-*0000;/mid5 24,25: high,med,low

15、=12b*-*0000;/mid3 26,27: high,med,low=12b*-*0000;/mid4 28,29,30,31: high,med,low=12b*-*0000;/mid5 32: high,med,low=12b*-*0000;/mid5 33: high,med,low=12b*-*0000;/mid6 34: high,med,low=12b*-*0000;/mid5 35: high,med,low=12b*-*0000;/mid4 36,37: high,med,low=12b*-*0000;/mid3 38,39: high,med,low=12b*-*000

16、0;/mid1 40: high,med,low=12b*-*0000;/mid5 41: high,med,low=12b*-*0000;/mid6 42: high,med,low=12b*-*0000;/mid5 43: high,med,low=12b*-*0000;/mid4 44,45: high,med,low=12b*-*0000;/mid3 46,47: high,med,low=12b*-*0000;/mid1 48,49: high,med,low=12b*-*0000;/mid2 50,51: high,med,low=12b*-*0101;/low5 52,53,54

17、,55: high,med,low=12b*-*0000;/mid1 56,56: high,med,low=12b*-*0000;/mid2 57,58: high,med,low=12b*-*0101;/low5 59,60,61,62,63: high,med,low=12b*-*0000;/mid1 default : high,med,low=12bx; endcase end endmodule 三、 曲目2模块 /bell2子模块康定情歌 module bell2 (inclk,beep3); input inclk; /系统时钟 output beep3; /蜂鸣器输出端 re

18、g 3:0high,med,low; reg 15:0origin; reg beep_r; /寄存器 reg 7:0state; reg 15:0count; assign beep3=beep_r; /输出音乐 /时钟频率6MHz reg clk_6MHz; reg 2:0 cnt1; always(posedge inclk) begin if(cnt13d4) cnt1=cnt1+3b1; else begin cnt1=3b0; clk_6MHz=clk_6MHz; end end /时钟频率4MHz reg clk_4Hz; reg 24:0 cnt2; always(posedg

19、e inclk) begin if(cnt225d*-*) cnt2=cnt2+25b1; else begin cnt2=25b0; clk_4Hz=clk_4Hz; end end always (posedge clk_6MHz) begin count = count + 1b1; /计数器加1 if(count = origin) begin count = 16h0; /计数器清零 beep_r = !beep_r; /输出取反 end end always(posedge clk_4Hz) begin case(high,med,low) b*-*0001:origin=*; /

20、低1 b*-*0010:origin=*; /低2 b*-*0011:origin=*; /低3 b*-*0101:origin=*; /低5 b*-*0110:origin=*; /低6 b*-*0111:origin=*; /中1 b*-*0000:origin=*; /中2 b*-*0000:origin=9101; /中3 b*-*0000:origin=7653; /中5 b*-*0000:origin=6818; /中6 b*-*0000:origin=5733; /高1 b*-*0000:origin=5108; /高2 b*-*0000:origin=4551; /高3 end

21、case end always (posedge clk_4Hz) begin if(state =103) state = 0; else state = state + 1; /康定情歌 case(state) 0,1: high,med,low=b*-*0000;/中3 2,3: high,med,low=b*-*0000;/中5 4,5: high,med,low=b*-*0000;/中6 6: high,med,low=b*-*0000;/中6 7: high,med,low=b*-*0000;/中5 8,9,10: high,med,low=b*-*0000;/中6 11: hig

22、h,med,low=b*-*0000;/中3 12,13,14,15: high,med,low=b*-*0000;/中2 16,17: high,med,low=b*-*0000;/中3 18,19: high,med,low=b*-*0000;/中5 20,21: high,med,low=b*-*0000;/中6 22: high,med,low=b*-*0000;/中6 23: high,med,low=b*-*0000;/中5 24,25: high,med,low=b*-*0000;/中6 26,27,28,29,30,31:high,med,low=b*-*0000;/中3 32

23、,33: high,med,low=b*-*0000;/中3 34,35: high,med,low=b*-*0000;/中5 36,37: high,med,low=b*-*0000;/中6 38: high,med,low=b*-*0000;/中6 39: high,med,low=b*-*0000;/中5 40,41,42: high,med,low=b*-*0000;/中6 43: high,med,low=b*-*0000;/中3 44,45,46,47: high,med,low=b*-*0000;/中2 48,49: high,med,low=b*-*0101;/中5 50,51

24、: high,med,low=b*-*0000;/中3 52: high,med,low=b*-*0000;/中2 53: high,med,low=b*-*0000;/中3 54: high,med,low=b*-*0000;/中2 55: high,med,low=b*-*0111;/1 56,57: high,med,low=b*-*0000;/中2 58,59,60,61,62,63:high,med,low=b*-*0110;/低6 64,65: high,med,low=b*-*0000;/中6 66,67,68,69,70,71:high,med,low=b*-*0000;/中2

25、 72,73: high,med,low=b*-*0101;/中5 74,75,76,77,78,79:high,med,low=b*-*0000;/中3 80: high,med,low=b*-*0000;/中2 81: high,med,low=b*-*0111;/1 82,83,84,85,86,87:high,med,low=b*-*0000;/中6 88,89: high,med,low=b*-*0101;/中5 90,91: high,med,low=b*-*0000;/中3 92: high,med,low=b*-*0000;/中2 93: high,med,low=b*-*00

26、00;/中3 94: high,med,low=b*-*0000;/中2 95: high,med,low=b*-*0111;/1 96,97: high,med,low=b*-*0000;/中2 98,99,100,101,102,103:high,med,low=b*-*0000;/中6 endcase end endmodule 四、 曲目3模块 /bell3子模块天空之城 module bell3 (inclk,beep4); input inclk; /系统时钟 output beep4; /蜂鸣器输出端 reg 3:0high,med,low; reg 15:0origin; re

27、g beep_r; /寄存器 reg 7:0state; reg 15:0count; assign beep4=beep_r; /输出音乐 /时钟频率6MHz reg clk_6MHz; reg 2:0 cnt1; always(posedge inclk) begin if(cnt13d4) cnt1=cnt1+3b1; else begin cnt1=3b0; clk_6MHz=clk_6MHz; end end /时钟频率4MHz reg clk_4Hz; reg 24:0 cnt2; always(posedge inclk) begin if(cnt225d*-*) cnt2=cn

28、t2+25b1; else begin cnt2=25b0; clk_4Hz=clk_4Hz; end end always (posedge clk_6MHz) begin count = count + 1b1; /计数器加1 if(count = origin) begin count = 16h0; /计数器清零 beep_r = !beep_r; /输出取反 end end always(posedge clk_4Hz) begin case(high,med,low) b*-*0001:origin=*; /低1 b*-*0010:origin=*; /低2 b*-*0011:origin=*; /低3 b*-*0100:origin=*; /低4 b*-*0101:origin=*; /低5 b*-*0110:origin=*; /低6 b*-*0111:origin=*; /低7 b*-*0111:origin=*; /中1 b*-*0000:origin=*; /中2 b*-*0000:origin