电子类英文翻译基于FPGA的分布式算法FIR滤波器设计Word文档下载推荐.docx

1、FIR滤波器的主要组成模块是乘累加单元（MAC），如果按照直观结构构造乘法器和系数寄存器来实现会占用大量的逻辑资源，显然不可取。本文采用基于分布式算法思想的方法来设计FIR滤波器，并在FPGA上实现。1 分布式算法原理分布式算法（distributed arithmetic，DA）最初是在1973年由Croisier提出的，但直到Xilinx发明FPGA的查找表以后，DA算法才在上世纪90年代初重新受到重视，并有效地应用在FIR滤波器的设计中。DA算法的原理如下。一线性时不变网络的输出为： （1）假设c（n）为已知常系数，x（n）是变量，用（B+1）位2进制补码表示为： （2）将（2）式代入（

2、1）式得： （3）函数f（c（n），xb（n）的实现方法是利用一个LUT（查找表）实现影射f（c（n），xb（n），也就是说2N字宽、预先设定程序的LUT接收一个N位输入向量xb=xb0，xb1xbN-1，输出为f（c（n），xb（n），个个影射，f（c（n），xb（n）都由相应的二次幂加权并累加。对于固定系数，整数乘以2b即左移6位，可以通过硬连线实现，不占用逻辑资源，利用图1所示的移位加法器就能有效地实现累加。DA算法的主要特点是巧妙利用SRAM查找表将固定系数的MAC运算转化为查表操作，其运算速度不随系数和输入数据精度的增加而降低，而且相对直接实现乘法器和系数寄存器在逻辑资源占用上得到了

3、极大的改善。缺点是查找表的大小随滤波器的阶数的增加呈指数增长，这时可以采用将大查找表分解为小查找表的方法来降低逻辑资源的消耗，如图2所示。图1 移位加法器DA结构图2 将表分割以产生简化规模的分布式算法2 FIR滤波器的网络结构N阶FIR滤波器相对于输入时间序列x（n）的输出表达式为： （4）即输出序列为单位脉冲相应h（n）与输入x（n）的卷积，由卷积关系可直接画出结构图，称之为直接型结构，如图3所示，该结构中共需要N个乘法器。图3 FIR滤波器直接型网络结构对于线性相位FIR滤波器，其单位取样响应是对称或反对称的，即： （5）利用对称性可以简化网络结构，当h（n）为偶对称且N为偶数时，（6）

4、其线性网络结构如图4所示，仅需N/Z个乘法器。图4 线性相位FIR滤波器结构3 FIR滤波器的硬件电路设计下面以一个32阶FIR带通滤波器为例说明硬件电路设计的方法和过程。3.1 设计指标采用频率：200 Hz 类型：带通上限截止频率：54.3 Hz 下限截止频率：46 Hz阶数：32阶 系数数据宽度：16位输入数据宽度：16位 输出数据宽度：3.2 滤波器的设计使用MATLAB 7.1软件中Filter Design&AnalysisTool，选取带通滤波器，Kaiser窗设计方法，设计出符合设计指标的32阶线性相位FIR滤波器，其幅频特性和相频特性如图5所示。图5 FIR滤波器的幅频和相位

5、特性滤波器的特征参数用16位二进制补码表示如下：3.3 硬件电路组成单元FIR滤波器的硬件电路包括数据位扩展、并串转换器、移位寄存器组、预相加单元、查找表单元、查表结果相加单元、移位累加单元、锁存输出单元、控制单元等，总的结构如图6所示。图6 32阶FIR滤波器仿真波形（1） 数据位扩展：由于输入数据要进行预相加，为了防止溢出，保证电路正常工作，采用符号位扩展，使输入数据由16位增加到17位。（2） 并串转换器：由于电路以串行方式工作，须将并行输入的数据转换为串行数据输入，且顺序是先输入低位（LSB），后输入高位（MSB）。（3） 移位寄存器组：其主要功能是用寄存器组存储输入序列，实现输入数据

6、的延时输出，存储的级数等于FIR滤波器的阶数减1，即31。移位寄存器组输出的数据和并串转换器输出的数据一起形成如图1中所示的输入数据阵列形式。（4） 预相加单元：利用FIR滤波器系数的对称性，按照图4所示的FIR滤波器线性网络结构，将相同滤波器系数相乘两个输入数据预先相加，这样相当于将滤波器的阶数减半，减小了硬件规模。预相加单元采用在位串行电路中广泛应用的串行加法器来实现。（5） 查找表单元：如前所述，LUT的规模随滤波器阶数的增加呈指数增长，当滤波器的阶数很大时，查找表的规模过于庞大。为了减小规模，可以将1个有16位地址总线的LUT分割，产生4个4位地址总线部分LUT，先分别对4个部分表查表

7、，再将结果相加。为防止相加时产生溢出，将16位查表输出经过1位符号扩展变为17位。（6） 查表结果相加单元：加法器是影响FIR滤波器性能的主要部件，其工作速度决定了FIR滤波器的效率，因此采用具有超前进位功能的流水线加法器。（7） 移位累加单元：得到的查表结果相当于一个部分积，移位累加单元将其与寄存器中的部分积相加，结果右移1位还放入寄存器中，直到所有的位数都查表结束。特别应注意，最高位查表得到的结果不是与上一个右移1位的部分积相加，而是相减。这里的加法器仍是采用具有超前进位功能的流水线加法器，作减法时，只需将被减数取补即可。（8） 锁存输出单元：加法器的输出不稳定，将其结果经过一锁存器得到稳

8、定的输出。（9） 控制单元：产生复位，时序等控制信号，控制电路的总体运行。3.4 电路仿真在ALTERA公司的MAX+PLUS2软件环境下，用硬件描述语言VHDL对上述FIR滤波器的模块进行编程描述，并仿真各模块的波形，最后将各模块综合起来下载到器件FLEX10KE中形成FIR滤波器。用MATLAB设计了一幅度为0.22的50 Hz的正弦波，用250 Hz的采样器对其采样，得到周期序列0，0.209 2，0.129 3，0.129 3，0.209 2，用16位二进制补码表示为：0000H，1ACBH，108DH，EF73H，E538H，将其输入到FIR滤波器的输入端，滤波器的输出如图6所示，实

9、验结果与理论计算一致。并取32位以后的输出结果，在MATLAB里绘制波形，如图7所示，可见，FPGA仿真结果正确，50 Hz的正弦波通过了FIR滤波器。图7 50HZ正弦波采样序列通过FIR滤波器仿真波形4 结 论本文所介绍的基于FPGA、采用分布式算法实现FIR滤波器的方法，在提高系统运行速度和节省硬件资源方面具有很大的优势。而且，通过改变阶数和查找表中的系数，还可以将此设计灵活地运用于实现高通、低通和带阻滤波器，可移植性较好。因此，这种方法在高速数字信号处理中将有很好的应用前景。附件2：外文原文（复印件）According to FPGA the filter design of the

10、distribute type calculate way FIRPrefaceThe FIR filter is a numeral signal processing the most basic component in the system, it can at assurance arbitrarily Pin characteristic of in the meantime have strict of line mutually Pin characteristic, in the meantime its unit blunt arouse to respond to is

11、limited, have no an importation to the outputs feedback, is stability of system.Therefore, FIR filter at correspondence, picture processing, the mode identify etc. the realm all have extensive of application.Currently the hardware realization of FIR filter have the following a few way:One kind is an

12、 usage list the slice be in general use numeral filter integrated circuit, this kind of electric circuit usage simple, but because of word long with rank number of specification less, not easy complete satisfy effective demand.Although can adoption many slice expand to satisfy request, meeting incre

13、ment physical volume and achievement consume, as a result be subjected to restriction in actually the application.Another is usage DSP chip.The DSP chip has appropriation of numeral signal processing the function be adjustable to use, realization the FIR filter be opposite simple, but because of pro

14、cedure in proper order performance, the speed be subjected to restriction.And, be same DSP chip of dissimilarity system of company, the its plait distance instruction will also have dissimilarity, development the period be longer.Returning to have 1 kind is an usage programmable logic spare part, FP

15、GA/CPLD.The FPGA has a rules whole of inner part logic piece the whole row with abundant of on-line resources, special in keeping with used for a tiny particle degree and Gao proceed together degree structure of FIR filter of realization, opposite at the string line operation predominance of in gene

16、ral use DSP chip to say, proceed together sex with can expand sex all better.FIR filter of main constitute a mold piece is multiply by tired add unit（MAC）, if according to keep machine and coefficient of the view structure structure multiplication to deposit a machine to realization will take up a g

17、reat deal of of logic resources, obviously cant take.This literary grace use calculate way the method of the thought according to the distribute type to design FIR filter, and on the FPGA realization.1 distribute type calculate way principleDistribute type calculate way（distributed arithmetic, DA） f

18、irst is at 1973 is put forward by the Croisier, but until Xilinx invention check of FPGA after seeking watch, DA calculate way just at last century the beginning of 90s is valued afresh, and availably application design in FIR filter in.The principle of DA calculate way as follows.A glimmer of const

19、ant output of network for: （2）Suppose c（n） in order to have already oftenned know coefficient, the x（n） is to change quantity, use（B+1）2 enter to make to repair stop-watch to show for:Go into（1） the type generation into the type（2）： （3）The realization method of function f（c（n）, xb（n） is make use of

20、a LUT（check to seek form） realization counterfeit f（c（n）, xb（n）, be also say 2 N word breadth, in advance enactment procedure of the LUT receive a N importation vector xb=xb0, xb1 xbN-1, output for the f（c（n）, xb（n）, each counterfeit, f（c（n）, xb（n） all from correspond of two Mi add power combine tir

21、ed add.For fix coefficient, the integral multiply a 2 b namely left shift 6, can pass a hard on-line realization, dont take up a logic resources, make use of diagram 1 show of move an adder ability availably realization tired add.The main characteristics of DA calculate way is skillful make use of t

22、he SRAM check to seek form will fix coefficient of MAC operation conversion in order to check watch operation, it operation speed not with coefficient and importation data accuracy of increment but lower, and opposite direct realization multiplication machine and coefficient deposit a machine in tak

23、ing up logic resources get biggest of improvement.The weakness is the size which check to seek form with the rank of the filter number of the increment present an index number growth, at this time can adoption will big check to seek form resolve for small check a method of seek the form to lower a l

24、ogic resources of consume, such as diagram 2 show.Diagram 1 move an adder DA structureDiagram 2 partition form with the creation simplification scale of distribute type calculate way2 The network structure of the FIR filterThe N rank FIR filter is opposite in time of importation the sequence x（n） ou

25、tput expression type for: （4）Namely output sequence for the unit pulse correspond h（n） with importation x（n） of book accumulate, is accumulate relation by book can direct painting structure diagram, call it as direct type structure, such as diagram 3 show, should structure in total demand N multipli

26、cation machine.Diagram 3 the FIR filter direct type network structureTo the line mutually FIR filter, its unit samplings respond to be symmetry or objection call, namely: （5）Make use of the symmetry can simplification network structure, be h（n） is accidentally symmetry and N is even number,It the li

27、ne network structure such as diagram 4 show, only need a multiplication machine.Diagram 4 lines mutually FIR filter structure3 The hardware electric circuit of the FIR filter designUnderneath with a 32 rank FIR bandpass filter for example elucidation hardware electric circuit design of method and pr

28、ocess.3.1 design index signadoption frequency:200 Hz type:Takethe upper limit close frequency:54.3 the Hz descend a limit to close frequency:rank number:32 rank coefficient data width:16importation data width:16 output data width:the design of 3.2 filtersThe Filter Design& AnalysisTool in usage MATL

29、AB 7.1 softwares, selection bandpass filter, the design method of the Kaiser window, design 32 rank line which match design index sign mutually FIR filter, it Pin characteristic with mutually Pin characteristic such as diagram 5 show.Diagram 5 the Pin of the FIR filter with mutually characteristicTh

30、e characteristic parameter of filter with 16 binary system repair stop-watch Be show as follows:3.3 hardware electric circuits constitute unitThe hardware electric circuit of FIR filter include a data to expand, combine string conversion machine, move to deposit a machine set and prepare to mutually add unit, check to seek a form and list dollar and check a form result to mutually add unit and move one tired add unit,