1、 目的 2、寻址方式0111寄存器寻址寄存器间址3、寄存器号R0R1004、指令对应的操作码和寻址方式 Ri 代表寄存器寻址 (Ri)代表寄存器间址操作码代表指令寻址方式000DEC001MOVR1,(R0)010ADD(R1),(R0)011SUBR1,R0100OR(R1) ,R0101AND110INC(R1)5模型机框图设计数据通路的设计 如下:图1 数据通路的设计6、微指令流程图 流程如图:图2 微指令流程图7、微指令格式设计需要用到的微信号的设置:控制信号描述D_ACC把暂存器D中的操作数,送至ACCC+D_ACC把暂存器C和D中的操作数相加之后,结果送至ACCCD_ACC把暂存器
2、C和D中的操作数相与之后,结果送至ACCD-C-ACC把暂存器D和C中的操作数相减之后,结果送至ACCDec_ACCACC内容减1Inc_ACCACC内容加1Load_MAR将总线上数据装载至MARLoad_MDR将总线上数据装载至MDRLoad_C将总线上数据装载至暂存器CLoad_D将总线上数据装载至暂存器DLoad_R0将总线上数据装载至寄存器R0Load_R1将总线上数据装载至寄存器R1Load_PC将总线上数据装载至程序计数器PCLoad_IR将总线上数据装载至IRR_NW读取,不可写。当R_NW无效且CS有效时,MDR内容存储于存储器CS片选。用MAR的内容设置存储器地址INC_P
3、CPC+1 并将结果存至PC中PC_bus用PC 内容驱动总线ACC_bus用ACC内容驱动总线R0_bus用R0内容驱动总线R1_bus用R1内容驱动总线MDR_bus用MDR内容驱动总线CvD_ACC把暂存器D和C中的操作数相或之后,结果送至ACC8、 微程序控制器设计如图:共25条微指令,28个微信号控制,该信号为1时执行对应的微操作。低五位为下地址。272625242322212019181716151413121098765 40微地址Load_PCCvD_ACCCDD-C_C+D_INC_DEC_D_ACC_busMDR_C_R1_R0_PC_Load_D_CMDRMAR_IR_R
4、1R_NW下地址100001000102000113110104111105111110010101000010010010001110011000110111101110001011111011000009、VHDL实现-CPU 头文件 cpu_defs LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;PACKAGE cpu_defs IS -定义程序包,包头,包体 TYPE opcode IS (dec, mov, add, sub, orr, andd, inc); -这个语句适合于定义一些用std_logic 等不方便定义的类型,综合器自动实现枚举类型
5、元素的编码,一般将第一个枚举量(最左边)编码为0 CONSTANT word_w: NATURAL :=12; CONSTANT op_w:=3; CONSTANT rfill: STD_LOGIC_VECTOR(op_w-1 downto 0):=(others =0); -FUNCTIOn slv2op(slv:IN STD_LOGIC_VECTOR) RETURN opcode; FUNCTION op2slv(op:in opcode) RETURN STD_LOGIC_VECTOR;END PACKAGE cpu_defs;PACKAGE BODY cpu_defs IS TYPE
6、optable IS ARRAY(opcode) OF STD_LOGIC_VECTOR(op_w-1 DOWNTO 0);-数组有5个元素,其他均0 CONSTANT trans_table:optable :=(000, 001010011100,101110IN opcode) RETURN STD_LOGIC_VECTOR IS BEGIN RETURN trans_table(op); END FUNCTION op2slv;END PACKAGE BODY cpu_defs;-微程序控制器实验 USE IEEE.STD_LOGIC_1164.ALL,IEEE.NUMERIC_STD
7、.ALL;USE WORK.CPU_DEFS.ALL;-使用自己定义的程序包ENTITY CPU ISPORT( clock : IN STD_LOGIC;-时钟 reset :-复位 mode : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -查看用 mem_addr : IN UNSIGNED (word_w-op_w-1 DOWNTO 0);-地址 output : OUT STD_LOGIC_VECTOR(word_w-1 DOWNTO 0); data_r_out : OUT STD_LOGIC_VECTOR(27 DOWNTO 0);-微指令R op_out
8、: OUT STD_LOGIC_VECTOR(op_w-1 DOWNTO 0);-操作码 add_r_out : OUT UNSIGNED(4 DOWNTO 0); -微地址R R1_OUT,R0_OUT : OUT STD_LOGIC_VECTOR(word_w-1 DOWNTO 0) );END ENTITY;ARCHITECTURE rtl OF CPU IS TYPE mem_array IS ARRAY (0 TO 2*(word_w-op_w)-1) OF STD_LOGIC_VECTOR(word_w-1 DOWNTO 0);-定义RAM SIGNAL mem : mem_arr
9、ay; CONSTANT prog : mem_array:=( -操作码&操作数个数&目的操作数寄存器号&寻址方式&源操作数寄存器号& 0= op2slv(dec) & 0&0100, 1= op2slv(mov) &111 2= op2slv(add) & 3= op2slv(sub) & 4= op2slv(orr) & 5= op2slv(andd) & 6= op2slv(inc) & 7= STD_LOGIC_VECTOR(TO_UNSIGNED(8,word_w), 8= STD_LOGIC_VECTOR(TO_UNSIGNED(7,word_w), OTHERS = (OTHE
10、RS =); TYPE microcode_array IS ARRAY (0 TO 25) OF STD_LOGIC_VECTOR(27 DOWNTO 0);CONSTANT code : microcode_array:=( -控制存储器 0=0000000000000100010000100001 1=0000000000000000000011000010 2=0000000001000000001000000011 3=0000000000000000000000011010, 4=0000000000000000000000011110 5=00000000000000000000
11、00011111 6=000000000000100100001100010000000000000010000100000010000000000000000000000011001001 9=0000000001000001000000000100 10=0000000000010010000000001110 11=0000000000010000010000001100 12=0000000000000000000011001101 13=0000000001000010000000001110 14=0000000000000000000000011101 15=0000000000
12、000000000000011000 16=0000001110000000000000010111,-DEC 17=0000000000100000000000010111,-MOV 18=0000100010000000000000010111,-ADD 19=0001000010000000000000010111,-SUB 20=0100000010000000000000010111,-OR 21=0010000110000000000000010111,-AND 22=0000010110000000000000010111,-INC 23=00000000000000000000
13、00011011 24=0000000000000000000100000000 25=0000000000000000100010000000 SIGNAL count : UNSIGNED(word_w-op_w-1 DOWNTO 0); SIGNAL op : STD_LOGIC_VECTOR(op_w-1 DOWNTO 0); SIGNAL z_flag : STD_LOGIC; SIGNAL mdr_out : STD_LOGIC_VECTOR(word_w-1 DOWNTO 0); SIGNAL mar_out : SIGNAL IR_out : SIGNAL acc_out :
14、UNSIGNED(word_w-1 DOWNTO 0); SIGNAL C_out : SIGNAL D_out : SIGNAL sysbus_out :BEGIN PROCESS(reset,clock) VARIABLE instr_reg : VARIABLE acc : CONSTANT zero : UNSIGNED(word_w-1 DOWNTO 0):=(OTHERS = VARIABLE mdr : VARIABLE mar : VARIABLE sysbus : VARIABLE microcode : microcode_array; VARIABLE add_r : U
15、NSIGNED(4 DOWNTO 0); VARIABLE data_r : STD_LOGIC_VECTOR(27 DOWNTO 0); VARIABLE temp : STD_LOGIC_VECTOR(4 DOWNTO 0); VARIABLE R0,R1 : STD_LOGIC_VECTOR(11 DOWNTO 0); VARIABLE C,D : BEGIN IF reset= THEN add_r : count instr_reg : acc : mdr : mar : mem = prog; sysbus : R0 := 000000001000; R1 :00000000100
16、1 C : D : z_flag = ELSIF RISING_EDGE(clock) THEN -microprogram controller data_r := code(TO_INTEGER(add_r); IF data_r(4 DOWNTO 0)=11010 THEN -判断下地址 temp:=0010 & instr_reg(6); add_r:= UNSIGNED(temp); ELSIF data_r(4 DOWNTO 0)=111110011 instr_reg(0); add_r:111100101 instr_reg(3);1110110 op(2 DOWNTO 0);110111100 ELSE add_r := UNSIGNED(data_r(4 DOWNTO 0); END IF; data_r_out =data_r; add_r_out = add_r; -PC IF data_r(14)=1 THEN -PC_bus= sysbus := rfill & STD
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