大连交通大学coa考试题3.docx

1、大连交通大学coa考试题3I. In multi-processor system,MEMI protocol is used to solve the problem of cache coherence,According to the given figure ,answer the following questions. Initial Snoopy1. This is the case of _ .2. Please finish drawing the figure3. With this case,please fill best answers into the follow

2、ing tabelThe states in beginThe states in endInitialSnoopyInitialSnoopy1 This is the case of Read Miss .3.The states in beginThe states in endInitialSnoopyInitialSnoopyIIInit read from memory,EIISInit read from memorySSIEInit read from memorySSIMSnoopy write back data to memory,Init read from memory

3、SSII. The following instruction:LOAD AC , X-Transfer the content of location X in memory to ACQuestion:1.Which addressing mode is included in this instruction?2.Please draw the figure of its addressing mode.3.Write down all the micro-operations and the control signals.1.direct addressing2. 3. Fetch

4、cycle:T1: (PC) MART2: (MAR) MEMORY READ MEMORYT3: MEMORY MBRT4: (MBR) IR (PC)+1 PCEXECUTE CYCLE:T1: AD(MBR) MART2: (MAR) MEMORY READ MEMORYT3: MEMORY MBRT4: (MBR) ACIII. A four-way set associative cache has 64k words and a line size of 8 words,Main memory has 4G words.Questions:1.What does four-way

5、set associative mapping mean?2.How to determine a cache hit/miss.3.Show the address mapping format.4.Where in the cache is the data from memory location 1FDB9753H and 1ABCD419H?(when read from memory).1.A given block in memory is mapped into any line of four lines in a fixed set.2.Coparing tag deter

6、mines cache hit on or hit miss3.memory size =4G words =232 length of RA=32-bitline size=8 words =23 words Word #=3-bitthe number of sets=64K word/8 word/4=2k=211 Set #=11-bit tag=32-11-3=18-bit Tag Set # Word #181134. 1FDB9753H =00,01 11,11 11,01 10,11 1001 0,111 0,101 0011 B 0 7 F 6 E H 2 E A HSet

7、#=2EAH Tag=07F6E H 1ABCD419H =00,01 10,10 10,11 11,00 1101 0,100 0,001 1001B 06AF3H 283H Set #=283 H Tag= 06AF3HIV. For the 8-bit data 1100,1011. Suppose when the data is read from memory,the check bits are calculated to be 0011.Questions:1.Please set up true value table to arrange data bits and che

8、ck bits2.Please make out the relationship of check bits and data bits.3.What are the check bits stored with data4.What is hamming code to be stored in memory5.What is the data that was read from memory.1100,1011Bit PositionPosition NumberCheck bitData bit121100D81111011D71101010D6091001D5081000C8070

9、111D4160110D3050101D2140100C4130011D1120010C2110001C102.C1=D1 D2 D4 D5 D7C2=D1 D3 D4 D6 D7C4=D2 D3 D4 D8C8=D5 D6 D7 D83.C1=11101=0 C2=10101=1C4=1011=1C8=0011=04.1100 0101 11105.SYNDROM WORD:0 1 1 00 0 1 1- 0 1 0 1=5 So D2 is wrong, the data that was read from memory is 1100,1001V. 1. Cache is used t

10、o solve the problem of speed between CPU and main memory2. Von Neumann machine had to be programmed manually in hardware.3.A byte always is 8 bits,but the length of a word is unfixed.4.Program counter is a register in CPU,it always point to the top of stack.5.Booths algorithm is used for sign-magnit

11、ude multiplication.6.The worst factor that limits the performance of instructon pipelining is conditional branch instruction.7.Write-back policy means write operantion to main memory as well as to cache8.Accumulator is the part of arithmetic and logic unit.9. In memory system ,there are four access

12、methods,cache is random access.10.The remainder is saved while executing ISR.Y N Y N N Y N N N YVI.1. Which doesnt belong to system bus?_A.address bus B.power lineC. data bus D.control bus2. Which answer about Hamming code is not true? A.the purpose of using hamming code only is detecting one-bit er

13、ror. B.using haming code can directly correct two-bit error. C.hamming code is aSingle-Error-Correcting code. D.hamming code is a Multiple-Error-Correcting code.3.Assume a 10-drive RAID configuration. In RAID1 level,storage density is_ A.90% B.80% C.60% D.50%4.Compared with RAID4 the advantage of RA

14、ID5 is _. A.Each disk operate independently. B.Large strips C. Parity is striped across all disks D. Data on fiailed dive can be reconstructed.5. In interrupt processing,CPU sends acknowledgement of interrut.The more important reason of CPUs acknowledgement is _. A. to let CPU get the vector from da

15、ta bus B.to let the I/O module remove request signal C. both A and B D. other aims6. When an I/O device completes an I/O operation in interrupt-driven I/O,the following sequence of hardware events occurs_. I/O module issues an interrupt signal to CPUCPU signal acknowledgment of interruptCPU finishes

16、 execution of current instructionCPU loads new PC value based on interruptCPU save PSW and PC to stackA. B. C. D. 7. Comparing with programmed I/O,interrupt-driven I/O further raises the usage rate of CPU operations,because_. A. it isnt necessary for CPU to save and restore scene B. it isnt necessar

17、y for CPU to intervene the data transfer C. it isnt necessary for CPU to read and check status repeatedly D. both A and B8. Which is the following description about overflow not true?_ A. Overflow occurs sometime in add and subtract arithmetic operation. B. Overflow and carriage is not different C.

18、Overflow can occur whether or not there is carry D. Overflow does not occur in multiplication operation of unsigned binary integer9. An 8-bit twos complement 0001 0011 is negated,then changed to a 16-bit that equal to _. A. 1000 0000 0001 0011 B. 0000 0000 0001 0011 C. 1111 1111 1110 1101 D. 1111 11

19、11 1110 110010. Compared with register indirect addressing mode, the disadvantage of indirect addressing mode is _. A. Large address space B. Multiple memory references C. Limit address space D. Less memory access11. RISC rejects _. A. few,simple addressing modes B. a limited and simple instrtuction

20、 sets C. few number of registers D. few,simple instruction formats12. At the end of fetch cycle micro-operations,the MAR contains_. A. instruction B. address of instruction C. operand D. address of operand13. Control unit use some input signals to produce control signals that open the gates of infor

21、mation paths and let the micro-operations implement, Which is NOT the input signal of control unit? A. clock and flags B. opcode in the instruction register C. interrupt request signal D. signals that cause data movement14. The Symmetric Multi-Processor(SMP)system is tightly coupled by_. A. high-spe

22、ed data-link and distributed memory B. shared RAIDs and high-speed data-link C. interconnect network and distributed memory D. distributed caches and shared memory15. The four states of “MESI” are _. A. Modified, Exclusive, Shared and Inclusive B. Modified,Exclusive,Shared and Invalid C. Modified,Ex

23、pected,Shared and Interrupted D. Moved,Exchanged,Shared and Invalid16. “Word” length means _. A.the number of binary code in a storage unit B. a combination of binary code in a storage unit C. the number of storage units D. the length of an operand17. Data processing is provided by _ which are the b

24、asic elements of computer. A. gates B. memory cells C. ALU D. CPU18. Word length of a computer is 32-bit,its storage cpacity is 64Kbyte.What is addressable range? _ A. 16KB B. 16K C. 32K D. 32KB19. Which is true the following statements?_ A. RAM is readable and writeable; data will be maintained whe

25、n power down B. RAM is a volatile,but static RAM is non-volatile C. EPROM is written,so it is a randow access memory D. EPROM is written,but is isnt random access memory20. On a movable head system,the time it takes for the beginning of the sector to reach the head is known as A. rotational delay B.

26、 seek time C. transfer time D. access time21. RAID levels 2 and 3 make use of a _technique. A. parallel access B.random access C. direct access D.independent access22. Which is true the following statements? _ A. interrupt has interrupt request,but DMA hasnt interrupt request. B. interrupt and DMA h

27、ave interrupt requests,but their aims arent same. C. DMA has interrupt requst,but interrupt hasnt interrupt request. D. interrupt and DMA have interrupt reuests, and their aims are same.23. In twos complement, two negative integers are added, when does overflow occurs?_ A. the sign of result is 0 B.

28、 the result has a carry bit C. the result has a carry bit D. cant determine24. In base register addressing ,the effective address of operand is _. A. (PC)+displacement B. (base register)+ displacement C. address field D. register25. _ is similar to direct addressing,but operand is held inregister na

29、med in address field of the instruction. A.displacement addressing B. stack addressing C. register indirect addressing D. register26. In an instruction,the number of address is one, the second address is implicit,usually is _. A. PC B.SP C.AC D.IR27. If an instruction includes four sub-cycles, a(n)

30、_occurs afer execute sub-cycle. A. fetch sub-cycle B.indirect sub-cycle C. interrupt sub-cycle D.cant determine28. On address mapping of cache, any block of main memory can be mapped to any line of cache it it _. A. associative mapping B.direct mapping C. set associative mapping D.random mapping29. The execution speed of addressing modes: