1、ALU实验报告 ALU实验设计报告 班号:28001020组员:方艳梅 2801311032 周秋彤 2800102005一、 实验目的(1)掌握ALU的一般结构设计(2)掌握复杂的时序电路设计二、 实验原理 ALU模块图ALU结构图加法器结构图:构成加法器的全加器:加法器结构图:减法器机构图:乘法器算法分析图:乘法器结构图:逻辑移位结构图:逻辑运算结构图:ALU共有五个输入端,一个输出端,a,b代表要处理的数据,为四比特,c为控制编码,为三比特,000代表需要ALU处理的这两个数据相加,001代表需要处理的是这两个数据想减,010代表需要处理的是这两个数据相乘,011代表要对a与b的后三位进
2、行逻辑运算,而逻辑运算的类型由a与b的第一位共同组成的一个二进制编码确定,00代表逻辑与,01代表逻辑或,10代表逻辑非,11代表逻辑异或,100代表对a进行逻辑移位,移位方式由b的第一位确定,1代表要对a进行左移,0代表要对a进行逻辑右移,而b的后三位决定要对a进行移位操作的位数,如b为1010代表要对a左移两位,其余的c无效。rst为复位控制,是一比特数据,且低电平使能。en为使能控制,也是一比特数据,为高电平使能。dout为按照输入要求操作后得出的数据,为八比特数据。在数据输入ALU后,按照c的编码选择相应的模块对a与b的值进行处理,最后通过多路选通器,对输出进行控制,输出需要输出的模块
3、。整个ALU计算过程需要四个时钟周期,其中输入占一个周期,计算占两个周期,输出占一个周期。在设计中,为了达到节能的目的,对每个模块定义了三个状态,开始计算(s0),计算中并等待下一次数据输入(s1),关闭(s2),即达到使用哪个模块就开启哪个模块的目的,算然增加了硬件开销,但大大地节约了能源。三、 实验内容代码如下:ALU:- Company: - Engineer: - - Create Date: 11:28:58 12/15/2009 - Design Name: - Module Name: alu - Behavioral - Project Name: - Target Devic
4、es: - Tool versions: - Description: - Dependencies: - Revision: - Revision 0.01 - File Created- Additional Comments: -library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primi
5、tives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity alu is port(clk,rst,en:in std_logic;a,b:in std_logic_vector(3 downto 0);c:in std_logic_vector(2 downto 0);dout:out std_logic_vector(7 downto 0);end alu;architecture Behavioral of alu iscomponent controller port(clk,rst,en:in std_l
6、ogic;a,b:in std_logic_vector(3 downto 0);c:in std_logic_vector(2 downto 0);dout:out std_logic_vector(7 downto 0);end component;signal a_r,b_r:std_logic_vector(3 downto 0);signal c_r:std_logic_vector(2 downto 0);signal dout_r:std_logic_vector(7 downto 0);begininst_controller:controller port map(clk=c
7、lk,rst=rst,en=en,a=a_r,b=b_r,c=c_r,dout=dout_r);process(rst,clk)begin if rst=1 then a_r=0000; b_r=0000; c_r=000; dout=00000000; elsif clkevent and clk=1 then if en=1 then a_r=a; b_r=b; c_r=c; doutclk,rst=rst_adder,en=en,a=a,b=b,dout=adder_dout);inst_subtracter:subtracter port map(clk=clk,rst=rst_sub
8、tracter,en=en,a=a,b=b,dout=subtracter_dout);inst_multiplier:multiplier port map(clk=clk,rst=rst_multiplier,en=en,a=a,b=b,dout=multiplier_dout);inst_logic:logic port map(clk=clk,rst=rst_logic,en=en,a=a,b=b,dout=logic_dout);inst_shift:shift port map(clk=clk,rst=rst_shift,en=en,a=a,b=b,dout=shift_dout)
9、;process(rst,clk)begin if rst=1 then c_b1=000; c_b2=000; elsif clkevent and clk=1 then if en=1 then c_b1=c; c_b2=c_b1; end if; end if;end process;process(rst,clk)begin if rst=1 then adder_s_p=s0; subtracter_s_p=s0; multiplier_s_p=s0; logic_s_p=s0; shift_s_p=s0; elsif clkevent and clk=1 then if en=1
10、then adder_s_p=adder_s; subtracter_s_p=subtracter_s; multiplier_s_p=multiplier_s; logic_s_p=logic_s; shift_s_p dout dout dout dout dout dout if c=000 then rst_adder=0; adder_s=s1; else rst_adder=1; adder_s if c=000 then rst_adder=0; adder_s=s1; else rst_adder=0; adder_s if c=000 then rst_adder=0; ad
11、der_s=s1; else rst_adder=0; adder_s null; end case;end process;process(c,subtracter_s_p)begin case subtracter_s_p is when s0 = if c=001 then rst_subtracter=0; subtracter_s=s1; else rst_subtracter=1; subtracter_s if c=001 then rst_subtracter=0; subtracter_s=s1; else rst_subtracter=0; subtracter_s if
12、c=001 then rst_subtracter=0; subtracter_s=s1; else rst_subtracter=0; subtracter_s null; end case;end process;process(c,multiplier_s_p)begin case multiplier_s_p is when s0 = if c=010 then rst_multiplier=0; multiplier_s=s1; else rst_multiplier=1; multiplier_s if c=010 then rst_multiplier=0; multiplier
13、_s=s1; else rst_multiplier=0; multiplier_s if c=010 then rst_multiplier=0; multiplier_s=s1; else rst_multiplier=0; multiplier_s null; end case;end process;process(c,logic_s_p)begin case logic_s_p is when s0 = if c=011 then rst_logic=0; logic_s=s1; else rst_logic=1; logic_s if c=011 then rst_logic=0;
14、 logic_s=s1; else rst_logic=0; logic_s if c=011 then rst_logic=0; logic_s=s1; else rst_logic=0; logic_s null; end case;end process;process(c,shift_s_p)begin case shift_s_p is when s0 = if c=100 then rst_shift=0; shift_s=s1; else rst_shift=1; shift_s if c=100 then rst_shift=0; shift_s=s1; else rst_sh
15、ift=0; shift_s if c=100 then rst_shift=0; shift_s=s1; else rst_shift=0; shift_s null; end case;end process;end Behavioral;加法器:- Company: - Engineer: - - Create Date: 10:48:30 12/15/2009 - Design Name: - Module Name: adder - Behavioral - Project Name: - Target Devices: - Tool versions: - Description:
16、 - Dependencies: - Revision: - Revision 0.01 - File Created- Additional Comments: -library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;
17、-use UNISIM.VComponents.all;entity adder is port(clk,rst,en:in std_logic;a,b:in std_logic_vector(3 downto 0);dout:out std_logic_vector(7 downto 0);end adder;architecture Behavioral of adder iscomponent full_adder port(a,b,cin:in std_logic;s,co:out std_logic);end component;signal a2_r,a3_r,a4_r: std_
18、logic;signal b2_r,b3_r,b4_r: std_logic;signal d0_r,d1_r:std_logic;signal c1_2_r:std_logic;signal dout_b:std_logic_vector(4 downto 0);signal c_b:std_logic_vector(4 downto 0);beginprocess(rst,clk)begin if rst=1 then a2_r=0; a3_r=0; a4_r=0; b2_r=0; b3_r=0; b4_r=0; c1_2_r=0; d0_r=0; d1_r=0; elsif clkevent and clk=1 then a2_r=a(2); a3_r=a(3); a4_r=
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