VHDL8位CPU设计包含程序Word格式文档下载.docx

1、ACC-XACCJMPGZ X05HIF ACC0 THEN XPC ELSE PC+1PCAND X06HACC and XACCOR X07HACC or XACCNOT X08HNot XACCSHIFTR X09HSHIFL ACC to RIGHT 1 bit, Logic ShiftSHIFTL X0AHSHIFT ACC to LEFT 1 bit, Logic ShiftMPY X 0BHACCHALT0CHHALT A PROGRAMA program is designed to test these instructions:Calculate the sum of al

2、l integers from 1 to 100.（1）, programming with C language:sum=0;temp=100;loop :sum=sum+temp;temp=temp-1;if temp=0 goto loop;end（2）, Assume in the RAM_DQ:sum is stored at location A4,temp is stored at location A3,the contents of location A0 is 0,the contents of location A1 is 1,the contents of locati

3、on A2 is 10010=6416.We can translate the above C language program with the instructions listed in Table 1 into the instruction program as shown in Table 2. Table 2 Example of a program to sum from 1 to 100Program with CProgram withinstructionsContents of RAM_DQ in HEXAddressContentsLOAD A00002A0STOR

4、E A40101A4temp=100LOAD A20202A2STORE A30301A3loop:LOOP:LOAD A40402A4ADD A30503A306LOAD A30702A3SUB A10804A1090 goto loop;JMPGZ LOOP0A0504end;0B0C000CA00000A10001A20064A3A4III. Internal Registers and MemoryMAR （Memory Address Register） MAR contains the memory location of the word to be read from the

5、memory or written into the memory. Here, READ operation is denoted as the CPU reads from memory, and WRITE operation is denoted as the CPU writes to memory. In our design, MAR has 8 bits to access one of 256 addresses of the memory.MBR （Memory Buffer Register）MBR contains the value to be stored in m

6、emory or the last value read from memory. MBR is connected to the address lines of the system bus. In our design, MBR has 16 Bits.PC （Program Counter）PC keeps track of the instructions to be used in the program. In our design, PC has 8 bits.IR （Instruction Register）IR contains the opcode part of an

7、instruction. In our design, IR has 8 bits.BR （Buffer Register）BR is used as an input of ALU, it holds other operand for ALU. In our design, BR has16 bits.LPM_RAM_DQLPM_RAM_DQ is a RAM with separate input and output ports. It works as a memory, and its size is 25616. Although its not an internal regi

8、ster of CPU, we need it to simulate and test the performance of CPU.LPM_ROMLPM_ROM is a ROM with one address input port and one data output port, and its size of data is 32bits which contains control signals to execute micro-operations.IV.ALUALU （Arithmetic Logic Unit） is a calculation unit which ac

9、complishes basic arithmetic and logic operations. In our design, some operations must be supported which are listed as follows:Table 3 ALU OperationsALU control signalOperationsExplanations3HADDACCACC+BR4HSUBACCACC- BR6HANDACCACC and BR7HORACCACC or BR8HNOTACCnot ACC9HSHIFTRACCShift ACC to Right 1 b

10、itSHIFTLACCShift ACC to Left 1 bitV. Micro-programmed Control UnitIn the Microprogrammed control, the microprogram consists of some microinstruction and the microprogram is stored in control memory that generates all the control signals required to execute the instruction set correctly. The microins

11、truction contains some micro-operations which are executed at the same time.Figure 2 shows the key elements of such an implementation.The set of microinstructions is stored in the control memory. The control address register contains the address of the next microinstructions to be read. When a micro

12、instruction is read from the control memory, it is transferred to a control buffer register. The register connects to the control lines emanating from the control unit. Thus, reading a microinstruction from the control memory is the same as executing that microinstruction. The third element shown in

13、 the figure is a sequencing unit that loads the control address register and issues a read command.Figure 2 Control Unit Micro-architecture（I）Total control signals for instructions are listed as follows:Table 4 Control signals for the micro-operationsBits in Control MemoryMicro-operationMeaningC0C7/

14、Branch AddressesC8PC0Clear PCC9PCPC+1Increment PCC10PCMBR7.0MBR7.0 to PCC11ACC0Clear ACCC12-C15ALU CONTROLControl operations of ALUC16RRead data from Memory to MBRC17WWrite data to Memory C18MARMBR7.0MBR7.0 to MAR as addressC19MARPCPC value to MARC20MBRACCACC value to MBRC21IRMBR15.8MBR15.8 to IR as

15、 opcodeC22BRMBRCopy MBR to BRC23CARCAR+1Increment CARC24CARC0C7C7C0 to CAR C25CAROPCODE+CARAdd OP to CARC26CAR0Reset CARC27-C31Not use-（II）The contents in rom.mif and the corresponding microprograms are listed as follows: 0 : 00810000; R1, CARCAR+1 1 : 00A00000; OPMBR15.8,CARCAR+1 2 : 02000000; CARC

16、AR+OP 3 : 01000014; CAR14H 4 : 01000019; CAR19H 5 : 0100001E; CAR1EH 6 : 01000023; CAR23H 7 : 01000041; CAR41H 8 : 01000028; CAR28H 9 : 0100002D; CAR2DH a : 01000032; CAR32H b : 01000037; CAR37H c : 0100003C; CAR3CH d : 01000046; CAR46H e : 0100004B; CAR4H f : 00000000; 14 : 00840000; MARMBR7.0, CAR

17、CAR+1 -STORE 15 : 00920200; MBRACC, PCPC+1,W1,CARCAR+1 16 : 04080000; CAR0 17 : 18 : 19 : MARMBR7.0, CARCAR+1 -LOAD 1a : 00810A00; PCPC+1,R1,ACC0,CARCAR+1 1b : 00C03000; BRMBR,ACCACC+BR, CARCAR+1 1c : 1d : 1e : MARMBR7.0, CARCAR+1 -ADD 1f : 00810200; PCPC+1,R1,CARCAR+1 20 : 21 : 22 : 23 : MARMBR7.0,

18、 CARCAR+1 -SUB 24 : 25 : 00C04000; BRMBR,ACCACC-BR, CARCAR+1 26 : 27 : 28 : MARMBR7.0, CARCAR+1 -AND 29 : 2a : 00C06000; BRMBR,ACCACC AND BR,CARCAR+1 2b : 2c : 2d : MARMBR7.0, CARCAR+1 -OR 2e : 2f : 00C07000; BRMBR,ACCACC OR BR, CARCAR+1 30 : 31 : 32 : MARMBR7.0, CARCAR+1 -NOT 33 : 00808200; PCPC+1,

19、 ACCNOT ACC,CARCAR+1 34 : 35 : 36 : 37 : MARMBR7.0, CARCAR+1 -SHIFTR 38 : 08092000; PCPC+1, ACCSHIFT ACC to Right 1 bit,CARCAR+1 39 : 3a : 3b : 3c : MARMBR7.0, CARCAR+1 -SHIFTL 3d : 0080A200; PCPC+1, ACCSHIFT ACC to Left 1 bit,CARCAR+1 3e : 3f : 40 : 41 : MARMBR7.0, CARCAR+1 -JMPGEZ 42 : 00805000; CARCAR+1, 43 : 44 : 45 : 46 : MARMBR7.0, CARCAR+1 -MPY 47 : 48 : 00C0B000; BRMBR,ACCACC*BR, CARCAR+1 49 : 4a : 4b : CAR4BH -HALT 4c :（III）The simulation waveforms of some operates1, load, add, store, halt （22+10）The contents in RAM:0 : 022A; Load 2A 032B; ADD 2B 012C; Store 2C 0C00; Ha