光伏发电逆变器毕业论文中英文资料外文翻译文献Word格式.docx

1、All 240x devices offer at least one event manager module which has been optimized for digital motor control and power conversion applications. Capabilities of this module include centered-and/or edge-alignedPWMgeneration,programmabledeadbandtoprevent shoot-through faults, and synchronized analog-to-

2、digital conversion. Devices with dual event managers enable multiple motor and/or converter control with a single240x DSP controller.The high performance, 10-bit analog-to-digital converter （ADC） has a minimum conversion time of 500 ns and offers up to 16 channels of analog input. The auto sequencin

3、g capability of the ADC allows a maximum of 16 conversions to take place in a single conversion session without any CPU overhead.A serial communications interface （SCI） is integrated on all devices to provide asynchronous communication to other devices in the system. For systems requiring additional

4、 communication interfaces; the 2407, 2406, and 2404 offer a 16-bit synchronous serial peripheral interface （SPI）. The 2407 and 2406 offer a controller area network （CAN） communications module that meets 2.0B specifications. To maximize device flexibility, functional pins are also configurable as gen

5、eral purpose inputs/outputs （GPIO）.To streamline development time, JTAG-compliant scan-based emulation has been integrated into all devices. This provides non-intrusive real-time capabilities required to debug digital control systems. A complete suite of code generation tools from C compilers to the

6、 industry-standard Code Composerdebugger supports this family. Numerous third party developers not only offer device-level development tools, but also system-level design and development support.PERIPHERALSThe integrated peripherals of the TMS320x240x are described in the following subsections:l Two

7、 event-manager modules （EVA, EVB）l Enhanced analog-to-digital converter （ADC） modulel Controller area network （CAN） modulel Serial communications interface （SCI） modulel Serial peripheral interface （SPI） modulel PLL-based clock modulel Digital I/O and shared pin functionsl External memory interfaces

8、 （LF2407 only）l Watchdog （WD） timer moduleEvent manager modules （EVA, EVB）The event-manager modules include general-purpose （GP） timers, full-compare/PWM units, capture units, and quadrature- encoder pulse （QEP） circuits. EV As and EVBs timers, compare units, and capture units function identically.

9、However, timer/unit names differ for EVA and EVB. Table 1 shows the module and signal names used. Table 1 shows the features and functionality available for the event-manager modules and highlights EVA nomenclature.Event managers A and B have identical peripheral register sets with EV A starting at

10、7400h and EVB starting at 7500h. The paragraphs in this section describe the function of GP timers, compare units, capture units, and QEPs using EVA nomenclature. These paragraphs are applicable to EVB with regard to functionhowever, module/signal names would differ.EVENT MANAGERMODULESEVAEVBSIGNALG

11、P TimersCompare UnitsTable 1. Module and Signal Names for EVA and EVBMODULETimer 1T1PWM/T1CMPTimer 3T3PWM/T3CMPTimer 2T2PWM/T2CMPTimer 4T4PWM/T4CMPCompare 1PWM1/2Compare 4PWM7/8Compare 2PWM3/4Compare 5PWM9/10Compare 3PWM5/6Compare 6PWM11/12Capture UnitsQEPExternal InputsDirection ExternalClockTDIRAT

12、CLKINADirectionExternal ClockTDIRBTCLKINBCapture 1CAP1Capture 4CAP4Capture 2CAP2Capture 5CAP5Capture 3CAP3Capture 6CAP6QEP1QEP3QEP2QEP4General-purpose （GP） timersThere are two GP timers: The GP timer x （x = 1 or 2 for EVA; x = 3 or 4 for EVB） includes:l A 16-bit timer, up-/down-counter, TxCNT, for r

13、eads or writesl A 16-bit timer-compare register, TxCMPR （double-buffered with shadow register）, for reads or writesl A 16-bit timer-periodregister, TxPR （double-buffered with shadow register）, for reads or writesl A 16-bit timer-control register,TxCON, for reads or writesl Selectable internal or ext

14、ernal input clocksl A programmable prescaler for internal or external clock inputsl Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer compare, and period interruptsl A selectable direction input pin （TDIR） （to count up or down when directional up-/down-count mode

15、is selected）The GP timers can be operated independently or synchronized with each other. The compare register associated with each GP timer can be used for compare function and PWM-waveform generation. There are three continuous modes of operations for each GP timer in up- or up/down-counting operat

16、ions. Internal or external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the time base for the other event-manager submodules: GP timer 1 for all the compares and PWM circuits, GP timer 2/1 for the capture units and the quadrature-pulse counting operatio

17、ns. Double-buffering of the period and compare registers allows programmable change of the timer （PWM） period and the compare/PWM pulse width as needed.Full-compare unitsThere are three full-compare units on each event manager. These compare units use GP timer1 as the time base and generate six outp

18、uts for compare and PWM-waveform generation using programmable deadband circuit. The state of each of the six outputs is configured independently. The compare registers of the compare units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed.Programmable deadb

19、and generatorThe deadband generator circuit includes three 8-bit counters and an 8-bit compare register. Desired deadband values （from 0 to 24 s） can be programmed into the compare register for the outputs of the three compare units. The deadband generation can be enabled/disabled for each compare u

20、nit output individually. The deadband-generator circuit produces two outputs （with orwithout deadband zone） for each compare unit output signal. The output states of the deadband generator are configurable and changeable as needed by way of the double-buffered ACTR register.PWM waveform generationUp

21、 to eight PWM waveforms （outputs） can be generated simultaneously by each event manager: three independent pairs （six outputs） by the three full-compare units with programmable deadbands, and two independent PWMs by the GP-timer compares.PWM characteristicsCharacteristics of the PWMs are as follows:

22、l 16-bit registersl Programmable deadband for the PWM output pairs, from 0 to 24 sl Minimum deadband width of 50 nsl Change of the PWM carrier frequency for PWM frequency wobbling as neededl Change of the PWM pulse widths within and after each PWM period as neededl External-maskable power and drive-

23、protection interruptsl Pulse-pattern-generatorcircuit,forprogrammablegenerationofasymmetric, symmetric, and four-space vector PWM waveformsl Minimized CPU overhead using auto-reload of the compare and period registersCapture unitThe capture unit provides a logging function for different events or tr

24、ansitions. The values of the GP timer 2 counter are captured and stored in the two-level-deep FIFO stacks when selected transitions are detected on capture input pins, CAPx （x = 1, 2, or 3 for EV A; and x = 4, 5, or 6 for EVB）. The capture unit consists of three capture circuits.Capture units includ

25、e the following features:l One 16-bit capture control register, CAPCON （R/W）l One 16-bit capture FIFO status register, CAPFIFO （eight MSBs are read-only, eight LSBs are write-only）l Selection of GP timer 2 as the time basel Three 16-bit 2-level-deep FIFO stacks, one for each capture unitl Three Schm

26、itt-triggered capture input pins （CAP1, CAP2, and CAP3） one input pin per capture unit. All inputs are synchronized with the device （CPU） clock. In order for a transition to be captured, the input must hold at its current level to meet two rising edges of the device clock. The input pins CAP1 and CA

27、P2 can also be used as QEPinputs to the QEP circuit.l User-specified transition （rising edge, falling edge, or both edges） detectionl Three maskable interrupt flags, one for each capture unitEnhanced analog-to-digital converter （ADC） moduleA simplified functional block diagram of the ADC module is shown in Figure 1. The ADC module consists of a 10-bit