DDS波形发生器VHDL源码Word下载.docx

1、-波形选择信号 00:正弦;01三角波;10方波;11不输出（恒为低电平）-DAOUT : out std_logic_vector（7 downto 0）;-8位DA输出模拟信号,直通方式,如需时钟控制则要修改DAOUTX:DAOUTY: out std_logic_vector（7 downto 0）;end;architecture DDS of DDS issignal ACC:std_logic_vector（ACCWidth-1 downto 0）:=（others =0signal DAOUT:std_logic_vector（7 downto 0）;beginprocess（C

2、LK,STEP）beginif（CLKevent and CLK=1） thenACC -正弦case ACC（ACCWidth-1 downto ACCWidth-8） is when 00000000 = DAOUT = 10000000;0000000110000011000000101000011000000011100010010000010010001101000001011001000000000110100100110000011110010110000010001001100100001001100111000000101010011111000010111010001000

3、001100101001010000110110101000000011101010101100001111101011100001000010110001000100011011010000010010101101110001001110111010000101001011110000010101101111110001011011000010000101111100010000011000110001110001100111001010000110101100110000011011110011110001110011010001000111011101010000011110110101

4、100001111111011000001000001101101100100001110111010010001011011111001000111110000100100100111000110010010111100101001001101110011100100111111010010010100011101010001010011110110000101010111011100010101111101111001011001111000100101101111100100010111011110100001011111111010100110000111101100011000111

5、110111001100101111100100110011111110100011010000110101111110110011011011111100001101111111110100111000111111100011100100111010111111110011101100111100001111010011111000111111010000000100000101000010010000110100010001000101010001100100011101001000010010010100101001001011010011000100110101001110010011

6、11010100000101000101010010010100110101010001010101010101100101011101011000010110010101101001011011010111000101110101011110010111110110000001100001011000100110001101100100011001010110011001100111011010000110100101101010011010110110110001101101011011100110111101110000011100010111001001110011011101000111010101110110011101110111100001111001011110100111101101111100011111010111111001111111100000011000001010000100100001011000011110001000100010101000101110001100100011101000111110010001 DAOU