AT91RM9200 K9K8 NAND FlashLinux驱动程序.docx

1、AT91RM9200 K9K8 NAND Flash Linux驱动程序AT91RM9200 K9K8* NAND Flash Linux驱动程序CPU：AT91RM9200NAND：K9K8G08不同容量的NAND需要做相应的调整，同时需要对控制脚相应的进行调整驱动程序如下，希望对需要的有所帮助，验证通过。/*File Name: char K9F1G_statu(void)description:writer: Liuxinminversion: 1.0date: 2009 10 20last chage: 2009 10 19*/#include #include #include #i

2、nclude #include #include #include #include #include #include #include /#include /#include #include #include #include #include #include #include #include /#include can0.h#include #include /*/#define K9F1G08R0A#define FLASH_READ_START 0x00 /read 1st. Cycle#define FLASH_READ_END 0x30 /read 2nd. Cycle#d

3、efine FLASH_READ_FOR_COPY_BANK_START 0x00 /Read for Copy Back 1st.cycle#define FLASH_READ_FOR_COPY_BANK_END 0x35 /Read for Copy Back 2nd.cycle#define FLASH_READ_ID 0x90 /read device id#define FLASH_RESET 0xFF /reset device#define FLASH_PAGE_PROGRAM_START 0x80 /Page Program 1st.cycle#define FLASH_PAG

4、E_PROGRAM_END 0x10 /Page Program 2nd.cycle#define FLASH_CACHE_PROGRAM_START 0x80 /Cache Program 1st.cycle#define FLASH_CACHE_PROGRAM_END 0x15 /Cache Program 2nd.cycle#define FLASH_COPY_BANK_PROGRAM_START 0x00 /Copy-Back Program 1st.cycle#define FLASH_COPY_BANK_PROGRAM_END 0x30 /Copy-Back Program 2nd

5、.cycle#define FLASH_BLOCK_ERASE_START 0x60 /EraseBlock 1st.cycle#define FLASH_BLOCK_ERASE_END 0xD0 /Erase Block end cyc#define FLASH_RANDOM_DATA_INPUT 0x85 /Random Data Input#define FLASH_RANDOM_DATA_OUTPUT_START 0x05 /Random Data Output 1st.cycle#define FLASH_RANDOM_DATA_OUTPUT_END 0xE0 /Random Dat

6、a Output 2nd.cyc#define FLASH_READ_STTUS 0x70 /Read Status#define K9F1G_ADDRESS_ADDRESS (0x40000000|(0x123)|(0x0122) /ADDRESS_ADDRESS#define K9F1G_COMMAND_ADDRESS (0x40000000|(0x123)|(0x0121) /COMMAND_ADDRESS#define K9F1G_DATA_ADDRESS (0x40000000|(0x1PIOC_ODSR = AT91C_PIO_PC3;AT91_SYS-PIOC_SODR = AT

7、91C_PIO_PC3;/PC3 should be low now/#define K9F1G_WE_LOW() AT91_SYS-PIOC_ODSR = 0; AT91_SYS-PIOC_SODR = AT91C_PIO_PC3;/PC3 should be high now/#define K9F1G_RE_HIGH() AT91_SYS-PIOC_ODSR = AT91C_PIO_PC1;AT91_SYS-PIOC_SODR = AT91C_PIO_PC1;/PC3 should be low now/#define K9F1G_RE_LOW() AT91_SYS-PIOC_ODSR

8、= 0; AT91_SYS-PIOC_SODR = AT91C_PIO_PC1;/*/declare the variasstatic unsigned int flash_address_add=0;static unsigned int flash_command_add=0;static unsigned int flash_data_add=0;/declare the function static int flash_ioctl(struct inode *, struct file *, unsigned int, unsigned long);static ssize_t fl

9、ash_read(struct file*, char*, size_t, loff_t*);static ssize_t flash_write(struct file*, const char*, size_t, loff_t*);static int flash_open(struct inode*, struct file*);static int flash_release(struct inode*, struct file*);struct file_operations flash_simon_fops = / owner: THIS_MODULE, ioctl: flash_

10、ioctl, write: flash_write, read: flash_read, open: flash_open, release: flash_release;static unsigned int FlashWriteAddress=0;static unsigned int FlashReadAddress=0;static unsigned int block_address = 0;/*function name: delay_flash(int nb)function description: delay the CPU not to do anything,just d

11、elayfunction.*/void delay_flash(int nb) while(nb-);/*Name: char K9F1G_statu(void)Function: get the K9F1G Busy or Ready statureturn: 1:ready 0:busywriter: Liuxinmindate:2009 10 20last chage:2009 10 20*/unsigned int K9F1G_statu(void) int statu; statu = (AT91_SYS-PIOC_PDSR ) & AT91C_PIO_PC15); return s

12、tatu;void K9F1G_CE_HIGH()#ifdef newboard AT91_SYS-PIOC_SODR = AT91C_PIO_PC13;#else AT91_SYS-PIOA_SODR = AT91C_PIO_PA0;#endifvoid K9F1G_CE_LOW()#ifdef newboard AT91_SYS-PIOC_CODR = AT91C_PIO_PC13; /clear the output reg#else AT91_SYS-PIOA_CODR = AT91C_PIO_PA0;#endifint K9F1G_READ_ID() int i; unsigned

13、char id5; /outb(FLASH_READ_ID,flash_command_add); printk( Physical address=%Xrn ,K9F1G_DATA_ADDRESS); printk( Physical address+131=%Xrn ,(K9F1G_DATA_ADDRESS+(131); printk( flash_command_add=%Xrn ,flash_command_add); printk( flash_address_add=%Xrn ,flash_address_add); printk( flash_data_add=%Xrn ,fla

14、sh_data_add); K9F1G_CE_LOW(); *(volatile unsigned char *)(flash_command_add)=FLASH_READ_ID; *(volatile unsigned char *)(flash_address_add)=0; while(0=K9F1G_statu(); /delay_flash(500); for(i=0;i5;i+) idi= *(volatile unsigned char *)(flash_data_add); while(0=K9F1G_statu(); K9F1G_CE_HIGH(); printk(the

15、NAND flash device id=); for(i=0;iPIOC_PER = AT91C_PIO_PC13; /enable the peripheral control AT91_SYS-PIOC_OER = AT91C_PIO_PC13; /output enable AT91_SYS-PIOC_SODR = AT91C_PIO_PC13;#if 0 /*init the PA0*/ AT91_SYS-PIOC_MDDR = AT91C_PIO_PC13; /disable the Multi function AT91_SYS-PIOC_PER = AT91C_PIO_PC13

16、; /enable the peripheral control AT91_SYS-PIOC_OER = AT91C_PIO_PC13; /output enable AT91_SYS-PIOC_IFDR = AT91C_PIO_PC13; /AT91_SYS-PIOA_CODR = AT91C_PIO_PA0; AT91_SYS-PIOC_IDR = AT91C_PIO_PC13; /disable the interrupt /AT91_SYS-PIOC_MDDR = AT91C_PIO_PC13; /disable the Multi function /AT91_SYS-PIOA_PP

17、UER = AT91C_PIO_PA0; /AT91_SYS-PIOA_OWER = AT91C_PIO_PA0; /enable write the PIO_ODSR for PA0 AT91_SYS-PIOC_SODR = AT91C_PIO_PC13; /AT91_SYS-PIOA_ODSR = AT91C_PIO_PA0; /*init the PC1 and PC3 for */*should init the PC1 and PC3 as SMC signal*/ AT91_SYS-PIOC_PER = AT91_SYS-PIOC_PER | AT91C_PIO_PC1 | AT91C_PIO_PC3; /enable the peripheral control AT91