EDA 硬件编程.docx
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EDA硬件编程
（1）CASE方式
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYs4to1IS
PORT（S0,S1:
INSTD_LOGIC;
A,B,C,D:
INSTD_LOGIC;
Y:
OUTSTD_LOGIC）;
ENDENTITY;
ARCHITECTUREslOFs4to1IS
SIGNALabc:
STD_LOGIC_VECTOR（1DOWNTO0）;
BEGIN
abc<=S1&S0;
PROCESS（abc,A,B,C,D）
BEGIN
CASEabcIS
WHEN"00"=>Y<=A;
WHEN"01"=>Y<=B;
WHEN"10"=>Y<=C;
WHEN"11"=>Y<=D;
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
ENDARCHITECTUREsl;
（1）IF—THEN方式
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYs4to1_2IS
PORT（S0,S1:
INSTD_LOGIC;
A,B,C,D:
INSTD_LOGIC;
Y:
OUTSTD_LOGIC）;
ENDENTITY;
ARCHITECTUREslOFs4to1_2IS
BEGIN
PROCESS（A,B,C,D,s0,s1）
BEGIN
IFs0='0'ANDs1='0'THENY<=A;
ELSIFs0='1'ANDs1='0'THEN
Y<=B;
ELSIFs0='0'ANDs1='1'THEN
Y<=C;
ELSEY<=D;
ENDIF;
ENDPROCESS;
ENDARCHITECTUREsl;
（2）
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmuxkIS
PORT（s0,s1,a1,a2,a3:
INSTD_LOGIC;
outY:
OUTSTD_LOGIC）;
ENDENTITY;
ARCHITECTUREmxOFmuxkIS
SIGNALy1,y2:
STD_LOGIC;
BEGIN
M1:
PROCESS（s0,a2,a3）
BEGIN
CASEs0IS
WHEN'0'=>y1<=a2;
WHEN'1'=>y1<=a3;
ENDCASE;
ENDPROCESS;
M2:
PROCESS（s1,a1,y1）
BEGIN
CASEs1IS
WHEN'0'=>y2<=a1;
WHEN'1'=>y2<=y1;
ENDCASE;
ENDPROCESS;
outY<=y2;
ENDARCHITECTUREmx;
（3）
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYdupIS
PORT（clk0,cl:
INSTD_LOGIC;
out1:
OUTSTD_LOGIC）;
END;
ARCHITECTUREddOFdupIS
SIGNALQ,D:
STD_LOGIC;
BEGIN
D<=NOT（CLORQ）;
PROCESS（clk0）
BEGIN
IFclk0'EVENTANDclk0='1'THEN
Q<=D;
ENDIF;
ENDPROCESS;
out1<=NOTQ;
END;
（4）
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYdupIS
PORT（clk,a,b:
INSTD_LOGIC;
q:
OUTSTD_LOGIC）;
END;
ARCHITECTUREddOFdupIS
SIGNALQ1,D:
STD_LOGIC;
BEGIN
D<=NOT（aANDb）;
PROCESS（clk）
BEGIN
IFclk'EVENTANDclk='1'THEN
Q1<=D;
ENDIF;
ENDPROCESS;
q<=Q1;
END;
（5）
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYNOT_ANDIS
PORT（a,b,c:
INSTD_LOGIC;
d:
OUTSTD_LOGIC）;
END;
ARCHITECTUREddOFNOT_ANDIS
SIGNALe,f:
STD_LOGIC;
BEGIN
e<=aANDb;
f<=eOR（NOTc）;
d<=aNANDf;
END;
（6）
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYyibuIS
PORT（d,clk,rst:
INSTD_LOGIC;
q:
OUTSTD_LOGIC）;
END;
ARCHITECTUREddOFyibuIS
SIGNALq0,q1,q2,q3:
STD_LOGIC;
BEGIN
PROCESS（clk,rst）
BEGIN
IFrst='1'THEN
q0<='0';
q1<='0';
q2<='0';
q3<='0';
ELSIFclk'EVENTANDclk='1'THEN
q0<=d;
q1<=q0;
q2<=q1;
q3<=q2;
ENDIF;
ENDPROCESS;
q<=q3;
END;
（6）累加计数器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYleijiaqiIS
PORT（clk,reset:
INSTD_LOGIC;
low,high:
OUTSTD_LOGIC_VECTOR（6DOWNTO0））;
END;
ARCHITECTUREbhvOFleijiaqiIS
SIGNALQ1,Q2:
INTEGER;
BEGIN
PROCESS（clk,reset）
BEGIN
IF（reset='1'）THEN
Q1<=0;
Q2<=0;
ELSIFclk'EVENTANDclk='1'THEN
IFQ1<9THEN
Q1<=Q1+1;
ELSEQ1<=0;
Q2<=Q2+1;
ENDIF;
ENDIF;
IFQ2>=9THEN
Q2<=0;
ENDIF;
ENDPROCESS;
OUT_1:
PROCESS（Q1）
BEGIN
CASEQ1IS
WHEN0=>low<="0111111";
WHEN1=>low<="0000110";
WHEN2=>low<="1011011";
WHEN3=>low<="1001111";
WHEN4=>low<="1100110";
WHEN5=>low<="1101101";
WHEN6=>low<="1111101";
WHEN7=>low<="0000111";
WHEN8=>low<="1111111";
WHEN9=>low<="1101111";
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESSOUT_1;
OUT_2:
PROCESS（Q2）
BEGIN
CASEQ2IS
WHEN0=>high<="0111111";
WHEN1=>high<="0000110";
WHEN2=>high<="1011011";
WHEN3=>high<="1001111";
WHEN4=>high<="1100110";
WHEN5=>high<="1101101";
WHEN6=>high<="1111101";
WHEN7=>high<="0000111";
WHEN8=>high<="1111111";
WHEN9=>high<="1101111";
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESSOUT_2;
ENDbhv;
（7）
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYzeroIS
PORT（in_shu:
INSTD_LOGIC_VECTOR（7DOWNTO0）;
out_zero:
OUTSTD_LOGIC_VECTOR（3DOWNTO0））;
END;
ARCHITECTUREbhvOFzeroIS
BEGIN
PROCESS（in_shu）
VARIABLEQ1:
STD_LOGIC_VECTOR（3DOWNTO0）;
BEGIN
Q1:
="0000";
FORiIN7DOWNTO0LOOP
IFin_shu（i）='0'THEN
Q1:
=Q1+1;
ELSEEXIT;
ENDIF;
ENDLOOP;
out_zero<=Q1;
ENDPROCESS;
ENDbhv;
（8）
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYTUIS
PORT（clk,reset,d:
INSTD_LOGIC;
q:
OUTSTD_LOGIC）;
ENDTU;
ARCHITECTUREbehvOFTUIS
TYPEstateIS（zero,one,two,three）;
SIGNALcurrent_state,next_state:
state;
BEGIN
PROCESS（reset,clk）
BEGIN
IFreset='1'THEN
current_state<=zero;
ELSIFclk'EVENTANDclk='1'THEN
current_state<=next_state;
ENDIF;
ENDPROCESS;
PROCESS（current_state）
BEGIN
CASEcurrent_stateIS
WHENzero=>q<='0';
IFd='0'THEN
next_state<=zero;
ELSEnext_state<=one;
ENDIF;
WHENONE=>q<='0';
IFd='0'THEN
next_state<=zero;
ELSEnext_state<=two;
ENDIF;
WHENtwo=>q<='0';
IFd='0'THEN
next_state<=zero;
ELSEnext_state<=three;
ENDIF;
WHENthree=>q<='1';
IFd='0'THEN
next_state<=zero;
ELSEnext_state<=three;
ENDIF;
ENDCASE;
ENDPROCESS;
END;
（9）
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYbijiaoIS
GENERIC（n:
INTEGER:
=8）;--定义类属参量及其数据类型
PORT（a,b:
INSTD_LOGIC_VECTOR（n-1DOWNTO0）;--用类属参量限制矢量长度
c:
OUTSTD_LOGIC_VECTOR（2DOWNTO0））;
END;
ARCHITECTUREbehavOFbijiaoIS
BEGIN
PROCESS（a,b）
VARIABLEint:
STD_LOGIC_VECTOR（2DOWNTO0）;
BEGIN
int:
="000";
FORiINa'LENGTH-1DOWNTO0LOOP--循环语句
IFa（i）=b（i）THENint:
="010";
ELSIFa（i）>b（i）THENint:
="100";EXIT;
ELSEint:
="001";EXIT;
ENDIF;
ENDLOOP;
c<=int;
ENDPROCESS;
END;
（10）
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYyouIS
PORT（clk,stop:
INSTD_LOGIC;
dout:
OUTSTD_LOGIC_VECTOR（7DOWNTO0））;
ENDyou;
ARCHITECTUREbehavOFyouIS
TYPEstateIS（a,ab,b,bc,c,cd,d,de,e,ef,f,fa）;
SIGNALpre_state,nx_state:
state;
SIGNALQ2:
INTEGER:
=0;
SIGNALQ1:
INTEGER:
=0;
SIGNALSTO:
INTEGER:
=80;
BEGIN
PROCESS（stop,clk）
BEGIN
IFstop='1'THEN
pre_state<=a;
ELSIFclk'EVENTANDclk='1'THEN
pre_state<=nx_state;
IFQ2<110THEN
Q2<=Q2+1;
ELSEQ2<=0;
ENDIF;
ENDIF;
Q1<=Q2;
ENDPROCESS;
PROCESS（pre_state）
BEGIN
CASEpre_stateIS
WHENa=>
dout<="00000001";
IFQ1<80THEN
nx_state<=a;
ELSEnx_state<=ab;
ENDIF;
WHENab=>
dout<="00000011";
IFQ1<110ANDQ1>80THEN
nx_state<=ab;
ELSEnx_state<=b;
ENDIF;
WHENb=>
dout<="00000010";
IFQ1<80THEN
nx_state<=b;
ELSEnx_state<=bc;
ENDIF;
WHENbc=>
dout<="00000110";
IFQ1<110ANDQ1>80THEN
nx_state<=bc;
ELSEnx_state<=c;
ENDIF;
WHENc=>
dout<="00000100";
IFQ1<80THEN
nx_state<=c;
ELSEnx_state<=cd;
ENDIF;
WHENcd=>
dout<="00001100";
IFQ1<110ANDQ1>80THEN
nx_state<=cd;
ELSEnx_state<=d;
ENDIF;
WHENd=>
dout<="00001000";
IFQ1<80THEN
nx_state<=d;
ELSEnx_state<=de;
ENDIF;
WHENde=>
dout<="00011000";
IFQ1<110ANDQ1>80THEN
nx_state<=de;
ELSEnx_state<=e;
ENDIF;
WHENe=>
dout<="00010000";
IFQ1<80THEN
nx_state<=e;
ELSEnx_state<=ef;
ENDIF;
WHENef=>
dout<="00110000";
IFQ1<110ANDQ1>80THEN
nx_state<=ef;
ELSEnx_state<=f;
ENDIF;
WHENf=>
dout<="00100000";
IFQ1<80THEN
nx_state<=f;
ELSEnx_state<=fa;
ENDIF;
WHENfa=>
dout<="00100001";
IFQ1<110ANDQ1>80THEN
nx_state<=fa;
ELSEnx_state<=a;
ENDIF;
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
END;
（11）
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYDCHUIS
PORT（a,clk1:
INSTD_LOGIC;
b:
OUTSTD_LOGIC）;
END;
ARCHITECTUREexn_behavOFDCHUIS
COMPONENTd
PORT（CLK:
INSTD_LOGIC;
DD:
INSTD_LOGIC;
Q:
OUTSTD_LOGIC）;
ENDCOMPONENT;
SIGNALX:
STD_LOGIC_VECTOR（7DOWNTO0）;
SIGNALY:
STD_LOGIC_VECTOR（7DOWNTO0）;
SIGNALZ:
STD_LOGIC_VECTOR（7DOWNTO0）;
BEGIN
gen:
FORiIN6DOWNTO1GENERATE
u1:
dPORTMAP（DD=>X（i）,CLK=>clk1,Q=>X（i+1））;
ENDGENERATEgen;
U2:
DPORTMAP（Q=>X
（1）,CLK=>clk1,DD=>a）;
U3:
DPORTMAP（DD=>X（7）,CLK=>clk1,Q=>b）;
END;
（12）
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYxingIS
PORT（clk:
INSTD_LOGIC;
outputs:
OUTSTD_LOGIC）;
ENDxing;
ARCHITECTUREbehvOFxingIS
TYPEFSM_STIS（s0,s1,s2,s3,s4,s5,s6,s7）;
SIGNALpre_state,nx_state:
FSM_ST;
BEGIN
PROCESS（clk）
BEGIN
IFclk='1'ANDclk'EVENTTHEN
pre_state<=nx_state;
ENDIF;
ENDPROCESS;
COM:
PROCESS（pre_state）
BEGIN
CASEpre_stateIS
WHENs0=>outputs<='0';
nx_state<=s1;
WHENs1=>outputs<='1';
nx_state<=s2;
WHENs2=>outputs<='0';
nx_state<=s3;
WHENs3=>outputs<='1';
nx_state<=s4;
WHENs4=>outputs<='1';
nx_state<=s5;
WHENs5=>outputs<='1';
nx_state<=s6;
WHENs6=>outputs<='0';
nx_state<=s7;
WHENs7=>outputs<='0';
nx_state<=s0;
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
ENDbehv;
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