数字系统仿真与VHDL课程设计报告.docx
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数字系统仿真与VHDL课程设计报告
数字系统仿真与VHDL课程设计报告
学院:
信息与电气工程学院
专业:
通信工程
班级:
通信一班
姓名:
李世辉
学号:
0804040102
指导老师:
张剑胡仕刚
设计时间:
2010.1.3—2010.1.14
目录
1.课程设计任务
2.课程设计目的
3.课程设计的基本要求
4.设计流程图
5.Max+plusII设计软件的基本操作
6.课程设计内容
七.课程设计心得体会
一.课程设计的任务
1.本次设计的任务是熟悉支持VHDL语言的软件,例如:
MAX—PLUS2,ISP,FOUNDATION等,利用这一类软件使用VHDL语言进行设计。
二.课程设计目的
1.熟练掌握相关软件的使用,操作。
能对VHDL语言程序进行编译,调试,以及通过计算机仿真,得到正确的仿真波形图,并根据所得仿真波形图分析判断并改进所设计的电路。
2.在成功掌握软件操作基础上,将所学数字电路的基础课知识与VHDL语言的应用型知识结合起来并与实际设计,操作联系起来,即“理论联系实际”。
3.深入了解VHDL语言的作用与价值,对用硬件语言设计一个电路系统开始具备一个较完整的思路与较专业的经验。
对EDA技术有初步的认识,并开始对EDA技术的开发创新有初步的理解。
三.设计的基本要求
1.熟悉数字电路及相关专业课程的基本知识并能联系具体程序
2.正确操作使用VHDL语言相关软件,能编译,调试,仿真VHDL语言程序
3.设计数字电路,编写程序,实现电路功能。
四.设计流程图
五.Max+plusII设计软件的基本操作
1.设计输入
原理图设计输入法
文本设计输入法
波形输入法
层次化设计输入法
2.项目编译
语法检查和设计规则检查
设计综合
生成编程数据文件
3.仿真和定时分析
仿真(Simulation)
定时分析(TimingAnalysis)
4.编程下载,调试与仿真
5.波形图的分析
六.课程设计内容
1.设计60进计数器
设计一个BCD码60进计数器。
要求实现同步,异步两种情况,且规定个位显示0~9,十位显示0~5,均用4位二进制数表示。
在此基础上试用VHDL语言描述中小规模集成电路74LS169。
(1).60进制同步计数器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYcount60tbIS
PORT(clk,w1c,w2c,cin:
INSTD_LOGIC;
cout:
OUTSTD_LOGIC;
data_in:
INSTD_LOGIC_VECTOR(3DOWNTO0);
ge:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
shi:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDENTITYcount60tb;
ARCHITECTUREexampleOFcount60tbIS
SIGNALge_n:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALshi_n:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
ge<=ge_n;
shi<=shi_n;
PROCESS(clk,w1c)IS
BEGIN
IF(W1C='1')THEN
ge_n<=data_in(3DOWNTO0);
ELSIF(clk'EVENTANDclk='1')THEN
IF(cin='1')THEN
IF(ge_n=9)THEN
ge_n<="0000";
ELSE
ge_n<=ge_n+'1';
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS(clk,w2c)IS
BEGIN
IF(w2c='1')THEN
shi_n<=data_in(3DOWNTO0);
ELSIF(clk'EVENTANDclk='1')THEN
IF(cin='1'ANDge_n=9)THEN
IF(shi_n=5)THEN
shi_n<="0000";
ELSE
shi_n<=shi_n+'1';
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS(clk,ge_n,shi_n)IS
BEGIN
IF(clk'EVENTANDclk='1')THEN
IF(ge_n=9ANDshi_n=5ANDcin='1')THEN
cout<='1';
ELSE
cout<='0';
ENDIF;
ENDIF;
ENDPROCESS;
ENDARCHITECTUREexample;
(2)60进制异步计数器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYcount60ybIS
PORT(clk,w1c,w2c,cin1:
INSTD_LOGIC;
cout2:
OUTSTD_LOGIC;
data_in:
INSTD_LOGIC_VECTOR(3DOWNTO0);
ge:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
shi:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDENTITYcount60yb;
ARCHITECTUREexampleOFcount60ybIS
SIGNALge_n:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALshi_n:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALcin2,cout1:
STD_LOGIC;
BEGIN
ge<=ge_n;
shi<=shi_n;
cin2<=cout1;
PROCESS(clk,w1c)IS
BEGIN
IF(W1C='1')THEN
ge_n<=data_in(3DOWNTO0);
ELSIF(clk'EVENTANDclk='1')THEN
IF(cin1='1')THEN
IF(ge_n=9)THEN
ge_n<="0000";
ELSE
ge_n<=ge_n+'1';
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS(cin2)IS
BEGIN
IF(w2c='1')THEN
shi_n<=data_in(3DOWNTO0);
ELSE
IF(cin2='1')THEN
IF(shi_n=5)THEN
shi_n<="0000";
ELSE
shi_n<=shi_n+'1';
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS(clk,ge_n,shi_n)IS
BEGIN
IF(clk'EVENTANDclk='1')THEN
IF(ge_n=9ANDcin1='1')THEN
cout1<='1';
ELSE
cout1<='0';
ENDIF;
IF(shi_n=5ANDcin2='1')THEN
cout2<='1';
ELSE
cout2<='0';
ENDIF;
ENDIF;
ENDPROCESS;
ENDARCHITECTUREexample;
(3)74LS169模块
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYls169IS
PORT(clk,wr,sel,cin:
INSTD_LOGIC;
cout:
OUTSTD_LOGIC;
data_in:
INSTD_LOGIC_VECTOR(3DOWNTO0);
data_out:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDENTITYls169;
ARCHITECTUREexampleOFls169IS
SIGNALdata:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
data_out<=data;
PROCESS(clk,wr)IS
BEGIN
IF(wr='1')THEN
data<=data_in(3DOWNTO0);
ELSIF(clk'EVENTANDclk='1')THEN
IF(cin='1')THEN
IF(sel='1')THEN
IF(data=15)THEN
data<="0000";
cout<='1';
ELSE
data<=data+'1';
cout<='0';
ENDIF;
ELSE
IF(data="0000")THEN
data<="1111";
cout<='1';
ELSE
data<=data-'1';
cout<='0';
ENDIF;
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
ENDARCHITECTUREexample;
2.循环彩灯控制器
设计一个循环彩灯控制器,该控制器控制红,绿,黄三个发光管循环点亮。
要求红发光管亮3秒,绿发光管亮2秒,黄发光管亮1秒。
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYxhcaidengIS
PORT(clk,clr:
INSTD_LOGIC;
red,green,yellow:
OUTSTD_LOGIC);
ENDENTITYxhcaideng;
ARCHITECTUREexampleOFxhcaidengIS
SIGNALdout:
STD_LOGIC_VECTOR(2DOWNTO0);
SIGNALm:
STD_LOGIC_VECTOR(2DOWNTO0);
BEGIN
red<=dout
(2);
green<=dout
(1);
yellow<=dout(0);
PROCESS(clk)IS
BEGIN
IF(clr='1')THEN
m<="001";
ELSIF(clk'EVENTANDclk='1')THEN
IF(m="110")THEN
m<="001";
ELSE
m<=m+1;
ENDIF;
CASEmIS
WHEN"001"=>dout<="100";
WHEN"010"=>dout<="100";
WHEN"011"=>dout<="100";
wHEN"100"=>dout<="010";
wHEN"101"=>dout<="010";
WHEN"110"=>dout<="001";
WHENOTHERS=>dout<="111";
ENDCASE;
ENDIF;
ENDPROCESS;
ENDARCHITECTURE;
3.数字显示的秒表
设计一块用数码管显示的秒表,能够准确的计时并显示。
最大计时为59秒,最小精确到0.1秒。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitymiaobiaois
port(clk:
instd_logic;
din:
instd_logic_vector(3downto0);
wr3,wr2,wr1:
instd_logic;
dout3:
outstd_logic_vector(3downto0);
dout2:
outstd_logic_vector(3downto0);
dout1:
outstd_logic_vector(3downto0));
endentitymiaobiao;
architectureexampleofmiaobiaois
signalout3:
std_logic_vector(3downto0);
signalout2:
std_logic_vector(3downto0);
signalout1:
std_logic_vector(3downto0);
begin
dout3<=out3;
dout2<=out2;
dout1<=out1;
process(clk)is
begin
if(clk'eventandclk='1')then
if(wr1='1')then
out1<=din;
elsif(out1="1001")then
out1<="0000";
else
out1<=out1+1;
endif;
endif;
endprocess;
process(clk)is
begin
if(clk'eventandclk='1')then
if(wr2='1')then
out2<=din;
elsif(out1="1001")then
if(out2="1001")then
out2<="0000";
else
out2<=out2+1;
endif;
endif;
endif;
endprocess;
process(clk)is
begin
if(clk'eventandclk='1')then
if(wr3='1')then
out3<=din;
elsif(out1="1001")then
if(out2="1001")then
if(out3="0101")then
out3<="0000";
else
out3<=out3+1;
endif;
endif;
endif;
endif;
endprocess;
endarchitectureexample;
4.设计一个2人抢答器
两人抢答,先抢为有效,用发光二极管显示是否抢到优先答题权。
答题结束后,按复位键可重新抢答下一题。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityanswer2is
port(reset:
instd_logic;
player:
instd_logic_vector(2downto1);
out1:
outstd_logic;
out2:
outstd_logic;
fail:
outstd_logic);
endentityanswer2;
architectureexampleofanswer2is
signala:
std_logic_vector(2downto0);
begin
out2<=a
(2);
out1<=a
(1);
fail<=a(0);
process(reset,player)is
begin
if(reset='0')then
a<="000";
else
caseplayeris
when"00"=>a<="000";
when"01"=>a<="010";
when"10"=>a<="100";
whenothers=>a<="001";
endcase;
endif;
endprocess;
endarchitectureexample;
5.交通灯控制器的程序设计
对所提供的交通灯实验程序进行改写,原来为两个相位的交通控制转变为四个相位,即:
东西直行,东西左转,南北直行,南北左转,加入一个方向显示灯的控制。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityjiaotongdengis
port(R1,G1,Y1,L1:
outstd_logic;
R2,G2,Y2,L2:
outstd_logic;
clk:
instd_logic);
endentityjiaotongdeng;
architectureexampleofjiaotongdengis
signalm:
std_logic_vector(6downto0):
="0000000";
signaln:
std_logic_vector(6downto0):
="0000000";
signala:
std_logic_vector(3downto0);
signalb:
std_logic_vector(3downto0);
begin
R1<=a(3);
G1<=a
(2);
Y1<=a
(1);
L1<=a(0);
R2<=b(3);
G2<=b
(2);
Y2<=b
(1);
L2<=b(0);
AA:
process(clk)is
begin
if(clk'eventandclk='1')then
if(m="1100100")then
m<="0000001";
else
m<=m+1;
endif;
if(m<=50)then
a<="1000";
elsif(m<=70)then
a<="0100";
elsif(m<=75)then
a<="0010";
elsif(m<=95)then
a<="0001";
else
a<="0010";
endif;
endif;
endprocess;
BB:
process(clk)is
begin
if(clk'eventandclk='1')then
if(n="1100100")then
n<="0000001";
else
n<=n+1;
endif;
if(n<=20)then
b<="0100";
elsif(n<=25)then
b<="0010";
elsif(n<=45)then
b<="0001";
elsif(n<=50)then
b<="0010";
else
b<="1000";
endif;
endif;
endprocess;
endarchitecture;
6.具有使能和清零作用的16进制计数器
libraryieee;
useieee.std_logic_1164.all;
entitycount16is
port(clk:
instd_logic;
clear:
instd_logic;
enable:
instd_logic;
outy:
outintegerrange0to15;
counter:
outstd_logic);
endentitycount16;
architecturebehaveofcount16is
begin
process(clk)
variablecnt:
integerrange0to15;
begin
if(clk'eventandclk='1')then
ifclear='0'then
cnt:
=0;
else
ifenable='1'then
cnt:
=cnt+1;
endif;
endif;
endif;
outy<=cnt;
ifcnt=15then
counter<='1';
else
counter<='0';
endif;
endprocess;
endbehave;
7.16路彩灯控制器
libraryieee;
useieee.std_logic_1164.all;
packagestate_packis
typestateis(qa,qb,qc,qd,qe,qf,qg);
endstate_pack;
libraryieee;
useieee.std_logic_1164.all;
usework.state_pack.all;
entitycontrollis
port(k,s,qc1,qc2,clk:
instd_logic;
y,k1,k2,k3,k4,k5,k6:
outstd_logic);
endcontroll;
architecturertlofcontrollis
signalcurrent_state:
state:
=qa;
begin
process
begin
waituntilclk'eventandclk='1';
ifs='0'then
y<='0';
else
y<='1';
endif;
ifk='0'then
k1<='0';k2<='0';k3<='1';
k4<='1';k5<='1';k6<='1';
current_state<=qa;
else
casecurrent_stateis
whenqa=>
current_state<=qb;
k1<='1';k3<='0';
whenqb=>
ifqc1='0'then
current_state<=qb;
else
current_state<=qc;
k1<='0';k2<='1';
endif;
whenqc=>
ifqc2='0'then
current_state<=qc;
else
current_state<=qd;
k4<='0';
endif;
whenqd=>
ifqc2='0'then
current_state<=qd;
else
current_state<=qe;
k1<='1';k2<='0';
endif;
whenqe=>
ifqc1='0'then
current_state<=qe;
else
c