eda课程设计VHDL语言数字时钟电子琴来自重庆大学电子信息工程.docx
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eda课程设计VHDL语言数字时钟电子琴来自重庆大学电子信息工程
rjy4600_cnt60_1—60进制计数器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrjy4600_cnt60_1is
port（clk:
instd_logic;
en:
instd_logic;
bcd10,bcd1:
bufferstd_logic_vector（3downto0）;
preset:
instd_logic;
co:
outstd_logic）;
endrjy4600_cnt60_1;
architecturertlofrjy4600_cnt60_1is
signalco_1:
std_logic;
begin
process（clk,preset）
begin
ifpreset='0'then
bcd1<="0000";
else
ifclk'eventandclk='1'then
ifen='1'then
ifbcd1="1001"then
bcd1<="0000";
else
bcd1<=bcd1+'1';
endif;
elseifbcd1="0000"then
bcd1<="1001";
else
bcd1<=bcd1-'1';
endif;
endif;
endif;
endif;
endprocess;
process（clk,preset,bcd1）
begin
ifpreset='0'then
bcd10<="0000";
co_1<='0';
else
ifclk='1'andclk'eventthen
ifen='1'then
ifbcd1="1000"andbcd10="0101"then
co_1<='1';
elsifbcd1="1001"andbcd10="0101"then
bcd10<="0000";
co_1<='0';
elsifbcd1="1001"then
bcd10<=bcd10+'1';
co_1<='0';
endif;
elseifbcd1="0001"andbcd10="0000"then
co_1<='0';
elsifbcd1="0000"andbcd10="0000"then
bcd10<="0101";
co_1<='1';
elsifbcd1="0000"then
bcd10<=bcd10-'1';
co_1<='0';
elseco_1<='0';
endif;
endif;
endif;
endif;
endprocess;
co<=notco_1;
endrtl;
rjy4600_cnt24：
—24进制计数器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrjy4600_cnt24is
port（clk:
instd_logic;
en:
instd_logic;
bcd10,bcd1:
bufferstd_logic_vector（3downto0））;
endrjy4600_cnt24;
architecturertlofrjy4600_cnt24is
begin
process（clk）
begin
ifclk'eventandclk='1'then
ifen='1'then
ifbcd1="1001"then
bcd1<="0000";
elsifbcd1="0011"andbcd10="0010"then
bcd1<="0000";
else
bcd1<=bcd1+'1';
endif;
elseifbcd1="0000"andbcd10="0000"then
bcd1<="0011";
elsifbcd1="0000"then
bcd1<="1001";
elsebcd1<=bcd1-'1';
endif;
endif;
endif;
endprocess;
process（clk,bcd1）
begin
ifclk='1'andclk'eventthen
ifen='1'then
ifbcd1="0011"andbcd10="0010"then
bcd10<="0000";
elsifbcd1="1001"then
bcd10<=bcd10+'1';
endif;
elseifbcd1="0000"andbcd10="0000"then
bcd10<="0010";
elsifbcd1="0000"then
bcd10<=bcd10-'1';
endif;
endif;
endif;
endprocess;
endrtl;
rjy4600_div1000：
—1000分频
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrjy4600_div1000is
port（clk:
instd_logic;
q:
outstd_logic）;
endrjy4600_div1000;
architecturertlofrjy4600_div1000is
signaldiv:
integer:
=0;
begin
process（clk）
begin
ifclk'eventandclk='1'then
ifdiv=999then
div<=0;q<='1';
else
div<=div+1;q<='0';
endif;
endif;
endprocess;
endrtl;
rjy4600_display：
—动态译码及显示扫描
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrjy4600_displayis
port（din0:
instd_logic_vector（3downto0）;
din1:
instd_logic_vector（3downto0）;
din2:
instd_logic_vector（3downto0）;
din3:
instd_logic_vector（3downto0）;
din4:
instd_logic_vector（3downto0）;
din5:
instd_logic_vector（3downto0）;
clk:
instd_logic;
led_sa:
outstd_logic;
led_sb:
outstd_logic;
led_sc:
outstd_logic;
led_a:
outstd_logic;
led_b:
outstd_logic;
led_c:
outstd_logic;
led_d:
outstd_logic;
led_e:
outstd_logic;
led_f:
outstd_logic;
led_g:
outstd_logic;
led_dp:
outstd_logic）;
endrjy4600_display;
architecturebehaveofrjy4600_displayis
signalseg:
std_logic_vector（6downto0）;
signalsel:
std_logic_vector（2downto0）;
signalnum:
std_logic_vector（3downto0）;
signals:
std_logic_vector（2downto0）;
begin
led_sa<=sel（0）;
led_sb<=sel
（1）;
led_sc<=sel
（2）;
led_a<=seg（0）;
led_b<=seg
（1）;
led_c<=seg
（2）;
led_d<=seg（3）;
led_e<=seg（4）;
led_f<=seg（5）;
led_g<=seg（6）;
process（clk）
begin
ifclk'eventandclk='1'then
ifs="101"then
s<="000";
else
s<=s+'1';
endif;
endif;
endprocess;
process（s,din0,din1,din2,din3,din4,din5）
begin
ifs="000"then
sel<="000";
num<=din0;
led_dp<='0';
elsifs="001"then
sel<="001";
num<=din1;
led_dp<='0';
elsifs="010"then
sel<="010";
num<=din2;
led_dp<='0';
elsifs="011"then
sel<="011";
num<=din3;
led_dp<='0';
elsifs="100"then
sel<="100";
num<=din4;
led_dp<='0';
elsifs="101"then
sel<="101";
num<=din5;
led_dp<='0';
else
sel<="XXX";
num<="XXXX";
led_dp<='0';
endif;
endprocess;
seg<="0111111"whennum=0else
"0000110"whennum=1else
"1011011"whennum=2else
"1001111"whennum=3else
"1100110"whennum=4else
"1101101"whennum=5else
"1111101"whennum=6else
"0000111"whennum=7else
"1111111"whennum=8else
"1101111"whennum=9else
"1110111"whennum=10else
"1111100"whennum=11else
"0111001"whennum=12else
"1011110"whennum=13else
"1111001"whennum=14else
"0000000"whennum=15else---1110001
"0000000";
endbehave;
rjy4600_keyin：
—按键输入模块
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrjy4600_keyinis
port（tm_ch:
instd_logic;
ch_h:
instd_logic;
ch_m:
instd_logic;
ch_s:
instd_logic;
clk_1:
instd_logic;
clk:
instd_logic;
a_d:
instd_logic;
co_60_1:
instd_logic;
co_60_2:
instd_logic;
o_q1:
outstd_logic;
o_q2:
outstd_logic;
o_q3:
outstd_logic;
o_en:
outstd_logic;
reset:
outstd_logic）;
endrjy4600_keyin;
architecturertlofrjy4600_keyinis
begin
process（clk,tm_ch,clk_1,co_60_2,co_60_1）
begin
ifclk'eventandclk='1'then
iftm_ch='1'then
o_en<='1';o_q3<=clk_1;o_q2<=co_60_2;o_q1<=co_60_1;reset<='1';--?
elseo_q1<=ch_h;o_q2<=ch_m;reset<=ch_s;o_q3<='0';
ifa_d='1'then
o_en<='1';
elseo_en<='0';
endif;
endif;
endif;
endprocess;
endrtl;
rjy4600_12_24：
12/24小时转换
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entityrjy4600_12_24is
port（c12_24:
instd_logic;
clk:
instd_logic;
chh:
instd_logic_vector（3downto0）;
ch:
instd_logic_vector（3downto0）;
chh_1:
outstd_logic_vector（3downto0）;
ch_1:
outstd_logic_vector（3downto0））;
endrjy4600_12_24;
architecturertlofrjy4600_12_24is
begin
process（c12_24,clk,chh,ch）
begin
ifclk='1'andclk'eventthen
ifc12_24='1'then
if（（chh="0001"andch>"0010"）or（chh="0010"））then
ifch<2thench_1<=ch+8;
elsechh_1<=chh-'1';ch_1<=ch-2;--ch_1<=ch-'1';--d_24<='0';
endif;
elsifchh="0000"andch="0000"then
chh_1<="0001";ch_1<="0010";
elsechh_1<=chh;ch_1<=ch;
endif;
elsechh_1<=chh;ch_1<=ch;
endif;
endif;
endprocess;
endrtl;
rjy4600_shan：
—闪烁模块
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrjy4600_shanis
port（clk_5:
instd_logic;
clk:
instd_logic;
s:
instd_logic;
xx:
instd_logic_vector（3downto0）;
x:
instd_logic_vector（3downto0）;
qq:
outstd_logic_vector（3downto0）;
q:
outstd_logic_vector（3downto0））;
endrjy4600_shan;
architecturertlofrjy4600_shanis
begin
process（clk,clk_5,xx,x,s）
begin
ifclk'eventandclk='1'then
ifs='0'then
ifclk_5='1'then
qq<="1111";
q<="1111";
elseqq<=xx;q<=x;
endif;
elseqq<=xx;q<=x;
endif;
endif;
endprocess;
endrtl;
rjy4600_baoshi：
—整点报时
ibraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrjy4600_baoshiis
port（clk50_1000:
instd_logic;
clk_1K:
instd_logic;
clk_2K:
instd_logic;
mm:
instd_logic_vector（3downto0）;
m:
instd_logic_vector（3downto0）;
ss:
instd_logic_vector（3downto0）;
s:
instd_logic_vector（3downto0）;
sound:
outstd_logic）;
endrjy4600_baoshi;
architecturertlofrjy4600_baoshiis
signaljishu:
integerrange0to50000;
signaljishu1:
integerrange0to50000;
begin
process（clk50_1000,mm,m,ss,s）
begin
ifclk50_1000'eventandclk50_1000='0'then
ifs>="0101"andss="0101"andm="1001"andmm="0101"then
ifjishu<20000then
sound<=clk_1K;
elsesound<='0';
endif;
ifjishu=49999then
jishu<=0;
elsejishu<=jishu+1;
endif;
elsifs="0000"andss="0000"andm="0000"andmm="0000"then
ifjishu<20000then
sound<=clk_2K;
elsesound<='0';
endif;
ifjishu=49999then
jishu<=0;
elsejishu1<=jishu1+1;
endif;
elsesound<='0';
endif;
endif;
endprocess;
endrtl;
rjy4600_naozhong：
—闹钟
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrjy4600_naozhongis
port（clk50_1000:
instd_logic;
naoz:
instd_logic;
hh:
instd_logic_vector（3downto0）;
h:
instd_logic_vector（3downto0）;
mm:
instd_logic_vector（3downto0）;
m:
instd_logic_vector（3downto0）;
ss:
instd_logic_vector（3downto0）;
s:
instd_logic_vector（3downto0）;
sound:
outstd_logic）;
endrjy4600_naozhong;
architecturertlofrjy4600_naozhongis
signalnz:
std_logic:
='0';
signalchh:
std_logic_vector（3downto0）;
signalch:
std_logic_vector（3downto0）;
signalcmm:
std_logic_vector（3downto0）;
signalcm:
std_logic_vector（3downto0）;
signalcss:
std_logic_vector（3downto0）;
signalcs:
std_logic_vector（3downto0）;
begin
process（clk50_1000）
begin
ifclk50_1000'eventandclk50_1000='0'then
ifnaoz='0'then
chh<=hh;ch<=h;cmm<=mm;cm<=m;css<=ss;cs<=s;
elseifchh=hhandch=handcmm=mmandcm=mandcss=ssthen---andcs=s
sound<='1';
elsesound<='0';
endif;
endif;
endif;
endprocess;
endrtl;
rjy4600_nzsound：
—闹钟响铃
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityrjy4600_nzsoundis
port（clk50_1000:
instd_logic;
clk_1K:
instd_logic;
clk_2K:
instd_logic;
--clk_1:
instd_logic;
naozhong_snd:
instd_logic;
sound:
outstd_logic）;
endrjy4600_nzsound;
architecturertlofrjy4600_nzsoundis
signaljishu:
integerrange0to50000;
signaljishu1:
integerrange0to50000;
signaldidi:
integerrange0to15:
=0;
begin
process（clk50_1000）
begin
ifclk50_1000'eventandclk50_1000='0'then
ifnaozhong_snd='1't
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