无效块建立程序.docx
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无效块建立程序
建立无效块程序
//程序功能：
完成一片FLASH无效块建立。
/*程序流程：
首先，读取每一块第一页和第二页第2048个字节数据，
将其分别存入ramA和ramB中；
然后，再把ramA和ramB中的数据进行比较，若同
时为FF，则该块有效，否则该块无效。
最后，将块地址加１，直到检查完整片FLASH的所有块为至，invalid_over=1表示整片FlASH//无效块建立完成。
*/
moduleinvalid_block_cesu（
clk,
rst,
start,
data_in,
cle,
ce1,
ce2,
we,
ale,
re,
wp,
data_out,
invalid_flash_link,
invalid_table_addr,
invalid_in,
invalid_table_flag,
invalid_over,
state）;
inputclk,rst,start;
input[7:
0]data_in;//FlASH反馈给FPGA的数据，检测
//I/O0的值，来说明各操作是否成功
outputcle,we,ale,re,wp,invalid_flash_link;
outputce1,ce2;
output[7:
0]data_out;//FPGA给FLASH的数据或地址
output[12:
0]invalid_table_addr; //无效块地址
outputinvalid_in; //每个块的无效块信息
outputinvalid_table_flag;//每个块无效块建立完成标志
outputinvalid_over; //整片FLASH无效块建立完成标志
output[4:
0]state;//无效块建立全过程的状态标志
regcle,we,ce,ale,re,wp;
reginvalid_flash_link,read_flag;
reg[7:
0]data_out;
reg[4:
0]state;
reg[9:
0]read_counter;
reg[33:
0]addr; //[33:
31]片选地址；
//[30:
18]块地址；
//[17:
12]页地址；
//[11:
0]每一页的2048个字节的地址
reg[1:
0]cnt;
reg[7:
0]ramA;//用来存每一块第一页第2048个字节的数据
reg[7:
0]ramB;//用来存每一块第二页第2048个字节的数据
reginvalid_in;
reginvalid_table_flag;
reginvalid_over;
reg[10:
0]wait_cycle;//执行完擦操作指令后的等待时间，
//即FLASH擦除每一块的需要的时间
wire[12:
0]invalid_table_addr;
wirece1,ce2; //一片FLASH的两个片选信号
assign invalid_table_addr=addr[30:
18];
//将内部addr赋于invalid_table_addr,
//给用于存储无效块信息的Ram
assignce1=（addr[33:
31]==3'd0）?
ce:
1;
//ce=0,选中FLASH第一小片
assignce2=（addr[33:
31]==3'd1）?
ce:
1;
//ce=1选中FLASH第二小片
parameterstep1=5'd0,
step2=5'd1,
step3=5'd2,
step4=5'd3,
step5=5'd4,
step6=5'd5,
step7=5'd6,
step8=5'd7,
step9=5'd8,
step10=5'd9,
step11=5'd10,
step12=5'd11,
step13=5'd12,
step14=5'd13,
step15=5'd14,
step16=5'd15,
step17=5'd16,
step18=5'd17,
step19=5'd18,
step20=5'd19,
step21=5'd20,
step22=5'd21,
step23=5'd22,
step24=5'd23,
step25=5'd24,
step26=5'd25,
step27=5'd26,
step28=5'd27;
always@（posedgeclk）
if（!
rst）
begin
state<=0;
cle<=1'b0;//命令锁存信号，高电平有效
ce<=1'b1;//片选信号，低电平有效
we<=1'b1;//写使能信号，低电平有效
ale<=1'b0;//地址锁存信号，高电平有效
re<=1'b1;//读使能信号，低电平有效
wp<=1'b0;//写保护信号，高电平有效
read_flag<=1'b0;
invalid_flash_link<=1'b0;
addr[33:
31]<=0;//片选初值
addr[30:
18]<=0;//块地址初值
addr[17:
12]<=0;//页地址初值
addr[11:
0]<=12'd2048;//页内地址第2048个字节初值
cnt<=0;
invalid_in<=0;
invalid_table_flag<=0;
ramA<=0;
ramB<=0;
invalid_over<=0;
wait_cycle<=0;
end
elseif（start==0）
begin
ce<=1'b1;
cle<=1'b0;
ce<=1'b1;
we<=1'b1;
ale<=1'b0;
re<=1'b1;
wp<=1'b0;
end
else
case（state）
step1:
begin
addr[33:
31]<=addr[33:
31];addr[30:
18]<=addr[30:
18];
addr[17:
12]<=addr[17:
12];
addr[11:
0]<=12'd2048;
cle<=1'b1;
ce<=1'b0;
we<=1'b0;//一个ClK，写使能信号翻转一次
ale<=1'b0;
re<=1'b1;
wp<=1'b0;
read_flag<=1'b0;
invalid_flash_link<=1'b0;
data_out<=8'h00;//读FLASH建立命令
invalid_in<=0;
invalid_table_flag<=0;
wait_cycle<=0;
invalid_over<=0;
state<=step2;
end
step2:
begin
cle<=1'b1;
ce<=1'b0;
we<=1'b1;
ale<=1'b0;
re<=1'b1;
read_flag<=1'b0;
invalid_flash_link<=1'b0;
state<=step3;
end
step3:
begin
cle<=1'b0;
ce<=1'b0;
we<=1'b0;
ale<=1'b1;
re<=1'b1;
read_flag<=1'b0;
invalid_flash_link<=1'b0;
data_out[7:
0]<=addr[7:
0];
//FPGA给FLASH列地址低8位
state<=step4;
end
step4:
begin
cle<=1'b0;
ce<=1'b0;
we<=1'b1;
ale<=1'b1;
re<=1'b1;
read_flag<=1'b0;
invalid_flash_link<=1'b0;
state<=step5;
end
step5:
begin
cle<=1'b0;
ce<=1'b0;
we<=1'b0;
ale<=1'b1;
re<=1'b1;
wp<=1'b0;
read_flag<=1'b0;
invalid_flash_link<=1'b0;
data_out[7:
4]<=4'd0;
data_out[3:
0]<=addr[11:
8];
//由FPGA给FLASH列地址高4位
state<=step6;
end
step6:
begin
cle<=1'b0;
ce<=1'b0;
we<=1'b1;
ale<=1'b1;
re<=1'b1;
invalid_flash_link<=1'b0;
state<=step7;
end
step7:
begin
cle<=1'b0;
ce<=1'b0;
we<=1'b0;
ale<=1'b1;
re<=1'b1;
data_out[7:
0]<=addr[19:
12];
//由FPGA给FLASH行地址低8位
invalid_flash_link<=1'b0;
state<=step8;
end
step8:
begin
cle<=1'b0;
ce<=1'b0;
we<=1'b1;
ale<=1'b1;
re<=1'b1;
invalid_flash_link<=1'b0;
state<=step9;
end
step9:
begin
cle<=1'b0;
ce<=1'b0;
we<=1'b0;
ale<=1'b1;
re<=1'b1;
wp<=1'b0;
invalid_flash_link<=1'b0;
data_out[7:
0]<=addr[27:
20];
//由FPGA给FLASH行地址次8位
state<=step10;
end
step10:
begin
cle<=1'b0;
ce<=1'b0;
we<=1'b1;
ale<=1'b1;
re<=1'b1;
invalid_flash_link<=1'b0;
state<=step11;
end
step11:
begin
cle<=1'b0;
ce<=1'b0;
we<=1'b0;
ale<=1'b1;
re<=1'b1;
invalid_flash_link<=1'b0;
data_out[7:
3]<=5'd0;
data_out[2:
0]<=addr[30:
28];
//由FPGA给FLASH行地址高3位
state<=step12;
end
step12:
begin
cle<=1'b0;
ce<=1'b0;
we<=1'b1;
ale<=1'b1;
re<=1'b1;
wp<=1'b0;
invalid_flash_link<=1'b0;
state<=step13;
end
step13:
begin
cle<=1'b1;
ce<=1'b0;
we<=1'b0;
ale<=1'b0;
re<=1'b1;
state<=step14;
data_out<=8'h30;//读确认命令
end
step14:
begin
cle<=1'b1;
ce<=1'b0;
we<=1'b1;
ale<=1'b0;
re<=1'b1;
state<=step15;
end
step15:
begin
cle<=1'b0;
ce<=1'b0;
we<=1'b1;
ale<=1'b0;
re<=1'b1;
data_out<=8'h0;
state<=step16;
end
step16:
begin
wait_cycle<=wait_cycle+1;
if（wait_cycle==11'd1500）
state<=step17;//读FLASH每一块内第一页或//第二页的第2048个字节数据的
//等待时间
elsestate<=step16;
end
step17:
begin
invalid_flash_link<=1'b1;
state<=step18;
end
step18:
begin
cle<=1'b0;
ce<=1'b0;
we<=1'b1;
ale<=1'b0;
re<=1'b0;
wp<=1'b0;
state<=step19;
end
step19:
begin
re<=1'b1;
state<=step20;
end
step20:
begin
state<=step21;
end
step21:
begin
ramA<=ramB;
//ramA中是每块第一页第2048个字节的数据
ramB<=data_in;
//ramB中是每块第二页第2048个字节的数据
cle<=1'b0;
ce<=1'b0;
we<=1'b1;
ale<=1'b0;
re<=1'b1;
state<=step22;
read_flag<=1'b1;
end
step22:
begin
cle<=1'b0;
ce<=1'b0;
we<=1'b1;
ale<=1'b0;
re<=1'b1;
cnt<=cnt+1;
addr[12]<=addr[12]+1;
//addr[12]只是在0与1之间变化，不产生进位，//为了读取每块第一页和第二页第2048个字节的
if（cnt==1）
begin
state<=step23;
cnt<=0;
end
else
state<=step1;
end
step23:
begin
cle<=1'b0;
ce<=1'b0;
we<=1'b1;
ale<=1'b0;
re<=1'b1;
read_flag<=1'b0;
invalid_flash_link<=1'b0;
if（ramA==8'hff&&ramB==8'hff）
//比较ramA与ramB的信息是否同时为FF
invalid_in<=1;
else
invalid_in<=0;
state<=step24;
end
step24:
begin
state<=step25;
end
step25:
begin
cle<=1'b0;
ce<=1'b0;
we<=1'b1;
ale<=1'b0;
re<=1'b1;
read_flag<=1'b0;
invalid_flash_link<=1'b0;
invalid_table_flag<=1;
ramA<=0;
ramB<=0;
state<=step26;
end
step26:
begin
invalid_table_flag<=0;
state<=step27;
end
step27:
begin
if（addr[33:
18]==16'd65535） //[33:
31]=3d’1;
begin//[30:
18]=13d’8192;
state<=step28;
invalid_over<=1;
//整片FLASH无效块建立完成标志拉高
end
else
begin
state<=step1;
addr[33:
18]<=addr[33:
18]+1;
invalid_in<=1'b0;
end
end
step28:
begin
state<=step28;
invalid_in<=0;
invalid_table_flag<=0;
cle<=1'b0;
ce<=1'b1;
we<=1'b1;
ale<=1'b0;
re<=1'b1;
wp<=1'b0;
end
default:
e
state<=step1;
endcase
endmodule
/********************建立无效块结束****************/
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