altera公司IP核使用手册.pdf

altera公司IP核使用手册.pdf

《altera公司IP核使用手册.pdf》由会员分享，可在线阅读，更多相关《altera公司IP核使用手册.pdf（76页珍藏版）》请在冰点文库上搜索。

101InnovationDriveSanJose,CAHyperTransportMegaCoreFunctionUserGuideMegaCoreVersion:

9.0DocumentDate:

March2009Copyright2009AlteraCorporation.Allrightsreserved.Altera,TheProgrammableSolutionsCompany,thestylizedAlteralogo,specificdevicedesignations,andallotherwordsandlogosthatareidentifiedastrademarksand/orservicemarksare,unlessnotedotherwise,thetrademarksandservicemarksofAlteraCorporationintheU.S.andothercountries.Allotherproductorservicenamesarethepropertyoftheirrespectiveholders.AlteraproductsareprotectedundernumerousU.S.andforeignpatentsandpendingap-plications,maskworkrights,andcopyrights.AlterawarrantsperformanceofitssemiconductorproductstocurrentspecificationsinaccordancewithAlterasstandardwarranty,butreservestherighttomakechangestoanyproductsandservicesatanytimewithoutnotice.Alteraassumesnoresponsibilityorliabilityarisingoutoftheapplicationoruseofanyinformation,product,orservicedescribedhereinexceptasexpresslyagreedtoinwritingbyAlteraCorporation.Alteracustomersareadvisedtoobtainthelatestversionofdevicespecificationsbeforerelyingonanypublishedinformationandbeforeplacingordersforproductsorservices.UG-MCHYPRTRNS-1.11March2009AlteraCorporationHyperTransportMegaCoreFunctionUserGuideContentsChapter1.AboutthisMegaCoreFunctionReleaseInformation.11DeviceFamilySupport.11Introduction.12Features.12OpenCorePlusEvaluation.13Performance.13Chapter2.GettingStartedDesignFlow.21MegaCoreFunctionWalkthrough.22CreateaNewQuartusIIProject.22LaunchtheMegaWizardPlug-inManager.23Step1:

Parameterize.25Step2:

SetUpSimulation.29Step3:

Generate.211SimulatetheDesign.213CompiletheDesign.213ProgramaDevice.214SetUpLicensing.215AppendtheLicensetoYourlicense.datFile.215SpecifytheLicenseFileintheQuartusIISoftware.215ExampleSimulationandCompilation.216ExampleQuartusIIProject.216ExampleSimulationwithTestVectors.216Chapter3.SpecificationsHyperTransportTechnologyOverview.31HTSystems.32HTFlowControl.33HyperTransportMegaCoreFunctionSpecification.33PhysicalInterface.34SynchronizationandAlignment.34ProtocolInterface.35ClockingOptions.37HyperTransportMegaCoreFunctionParametersandHTLinkPerformance.310Signals.314CSRModule.331OpenCorePlusTime-OutBehavior.340AppendixA.ParametersIntroduction.A1ParameterLists.A1DeviceFamilyandReadOnlyRegisters.A1BaseAddressRegisters.A2ClockingOptions.A3AdvancedSettings.A3ivContentsHyperTransportMegaCoreFunctionUserGuideMarch2009AlteraCorporationAppendixB.StratixDevicePinAssignmentsIntroduction.B1Guidelines.B1AppendixC.ExampleDesignGeneralDescription.C1AdditionalInformationRevisionHistory.Info1HowtoContactAltera.Info1TypographicConventions.Info2March2009AlteraCorporationHyperTransportMegaCoreFunctionUserGuidePreliminary1.AboutthisMegaCoreFunctionReleaseInformationTable11providesinformationaboutthisreleaseoftheHyperTransportMegaCorefunction.AlteraverifiesthatthecurrentversionoftheQuartusIIsoftwarecompilesthepreviousversionofeachMegaCorefunction.AnyexceptionstothisverificationarereportedintheMegaCoreIPLibraryReleaseNotesandErrata.AlteradoesnotverifycompilationwithMegaCorefunctionversionsolderthanonerelease.DeviceFamilySupportMegaCorefunctionsprovideeitherfullorpreliminarysupportfortargetAlteradevicefamilies:

FullsupportmeanstheMegaCorefunctionmeetsallfunctionalandtimingrequirementsforthedevicefamilyandmaybeusedinproductiondesigns.PreliminarysupportmeanstheMegaCorefunctionmeetsallfunctionalrequirements,butmaystillbeundergoingtiminganalysisforthedevicefamily;itmaybeusedinproductiondesignswithcaution.Table12showsthelevelofsupportofferedbytheHyperTransportMegaCorefunctionforeachoftheAlteradevicefamilies.Table11.HyperTransportMegaCoreFunctionReleaseInformationItemDescriptionVersion9.0ReleaseDateMarch2009OrderingCodeIP-HTProductID（s）0098VendorID（s）6AF7Table12.DeviceFamilySupportDeviceFamilySupportHardCopyStratixFullStratixFullStratixIIFullStratixIIGXPreliminaryStratixGXFullOtherdevicefamiliesNosupport12Chapter1:

AboutthisMegaCoreFunctionIntroductionHyperTransportMegaCoreFunctionUserGuideMarch2009AlteraCorporationPreliminaryIntroductionTheHyperTransportMegaCorefunctionimplementshigh-speedpackettransfersbetweenphysical（PHY）andlink-layerdevices,andisfullycompliantwiththeHyperTransportI/OLinkSpecification,Revision1.03.ThisMegaCorefunctionallowsdesignerstointerfacetoawiderangeofHyperTransporttechnology（HT）enableddevicesquicklyandeasily,includingnetworkprocessors,coprocessors,videochipsets,andASICs.FeaturesTheHyperTransportMegaCorefunctionhasthefollowingfeatures:

8-bitfullyintegratedHTend-chaininterfacePacket-basedprotocolDualunidirectionalpoint-to-pointlinksUpto16Gigabitspersecond（Gbps）throughput（8Gbpsineachdirection）200,300,and400MHzDDRlinksinStratixandStratixGXdevices200,300,400,and500MHzDDRlinksinStratixIIandStratixIIGXdevicesLow-swingdifferentialsignalingwith100-differentialimpedanceHardwareverifiedwithHyperTransportinterfacesonmultipleindustrystandardprocessorandbridgedevicesFullyparameterizedMegaCorefunctionallowsflexible,easyconfigurationFullyoptimizedfortheAlteraStratixII,Stratix,StratixGX,andStratixIIGXdevicefamiliesApplication-sideinterfaceusestheAlteraAtlanticTMinterfacestandardManagesHTflowcontrol,optimizingperformanceandeaseofuseIndependentbufferingforeachHTvirtualchannelAutomatichandlingofHTorderingrulesStallingofonevirtualchanneldoesnotdelayothervirtualchannels（subjecttoorderingrules）Flexibleparameterizedbuffersizes,allowingcustomizationdependingonsystemrequirementsUserinterfacehasindependentinterfacesfortheHTvirtualchannels,allowingindependentuserlogicdesignCyclicredundancycode（CRC）generationandcheckingtopreservedataintegrityIntegrateddetectionandresponsetocommonHTerrorconditionsCRCerrorsEnd-chainerrorsFullyintegratedHTconfigurationspaceincludesallrequiredconfigurationspaceregistersandHTcapabilitieslistregistersChapter1:

AboutthisMegaCoreFunction13PerformanceMarch2009AlteraCorporationHyperTransportMegaCoreFunctionUserGuidePreliminary32-bitand64-bitsupportacrossallbaseaddressregisters（BARs）AutomaticallyhandlesallCSRspaceaccessesVerilogHDLandVHDLsimulationsupportOpenCorePlusEvaluationWiththeAlterafreeOpenCorePlusevaluationfeature,youcanperformthefollowingactions:

Simulatethebehaviorofamegafunction（AlteraMegaCorefunctionorAMPPmegafunction）withinyoursystemVerifythefunctionalityofyourdesign,aswellasquicklyandeasilyevaluateitssizeandspeedGeneratetime-limiteddeviceprogrammingfilesfordesignsthatincludeMegaCorefunctionsProgramadeviceandverifyyourdesigninhardwareYouonlyneedtopurchasealicensefortheMegaCorefunctionwhenyouarecompletelysatisfiedwithitsfunctionalityandperformance,andwanttotakeyourdesigntoproduction.fFormoreinformationaboutOpenCorePlushardwareevaluationusingtheHyperTransportMegaCorefunction,referto“OpenCorePlusTime-OutBehavior”onpage340andAN320:

OpenCorePlusEvaluationofMegafunctions.PerformanceTheHyperTransportMegaCorefunctionuses20differentialI/Opinpairsand2single-endedI/Opins,requiring42pinstotal.Table13throughTable15showtypicalperformanceandadaptivelook-uptable（ALUT）orlogicelement（LE）usagefortheHyperTransportMegaCorefunctioninStratixIIGX,StratixII,Stratix,andStratixGXdevicesrespectively,usingtheQuartusIIsoftwareversion7.1.Table13showsthemaximumsupporteddataratesinmegabitspersecond（Mbps）bydevicefamilyandspeedgrade.Table13.MaximumSupportedHyperTransportDataRates（Note1）DeviceFamilySpeedGrade-3-4-5-6-7-8StratixIIGXdevices1000Mbps1000Mbps800MbpsN/A

（2）N/A

（2）N/A

（2）StratixIIdevices1000Mbps1000Mbps800MbpsN/A

（2）N/A

（2）N/A

（2）Stratixdevices（Flip-Chippackages）N/A

（2）N/A

（2）800Mbps800Mbps600Mbps400MbpsStratixdevices（WireBondpackages）N/A

（2）N/A

（2）N/A

（2）600Mbps400Mbps400MbpsStratixGXdevicesN/A

（2）N/A

（2）800Mbps800Mbps600MbpsN/A

（2）NotestoTable13:

（1）Ratesareperinterfacebit.Multiplybyeighttocalculatetheuni-directionaldatarateofan8-bitinterface.

（2）Devicesofthisspeedgradearenotofferedinthisdevicefamily.14Chapter1:

AboutthisMegaCoreFunctionPerformanceHyperTransportMegaCoreFunctionUserGuideMarch2009AlteraCorporationPreliminaryTable14showsperformanceanddeviceutilizationfortheHyperTransportMegaCorefunctioninStratixIIandStratixIIGXdevices.Table15showsperformanceanddeviceutilizationfortheHyperTransportMegaCorefunctioninStratixandStratixGXdevices.Table14.HyperTransportMegaCoreFunctionPerformanceinStratixIIandStratixIIGXDevicesParametersCombinationalALUTs

（2）LogicRegistersMemoryHTLinkfMAX（MHz）（3）UserInterfacefMAX（MHz）（3）RxPostedBuffersRxNon-PostedBuffersRxResponseBuffersClockingOption

（1）M4KM512844SharedRx/Tx/Ref3,5005,200120500125（4）844SharedRef/Tx3,5005,200140500125（4）844SharedRx/Tx3,6005,400160500150888SharedRx/Tx4,0006,0001605001501688SharedRx/Tx/Ref4,1006,200120500125（4）1688SharedRef/Tx4,1006,200140500125（4）1688SharedRx/Tx4,2006,400160500150NotestoTable14:

（1）Referto“ClockingOptions”onpage37formoreinformationabouttheseoptions.

（2）Otherparameters（BARconfigurations,etc.）varytheALUTandLogicRegisterutilizationnumbersbyapproximately+/-200.（3）Figuresfor-3speedgradedevicesonly.（4）WhenusingtheSharedRx/Tx/RefandSharedRef/Txoptions,theuserinterfacefrequencyislimitedtoexactlytheHTfrequenc