EDA技术与VHDL课后答案第3版潘松 黄继业.docx
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EDA技术与VHDL课后答案第3版潘松黄继业
第3章VHDL基础
习题
3-1如图所示
3-2程序：
IF_THEN语句
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmux21S
PORT（s1,s0:
INSTD_LOGIC_VECTOR;
a,b,c,d:
INSTD_LOGIC;
y:
OUTSTD_LOGIC）;
ENDENTITYmux21;
ARCHITECTUREoneOFmux21IS
BEGIN
PROCESS（s0,s1,a,b,c,d）
BEGIN
IFs1=’0’ANDs0=’0’THENy<=a;
ELSIFs1=’0’ANDs0=’1’THENy<=b;
ELSIFs1=’1’ANDs0=’0’THENy<=c;
ELSIFs1=’1’ANDs0=’1’THENy<=d;
ELSEy<=NULL;
ENDIF;
ENDPROCESS;
ENDARCHITECTUREone;
CASE语句
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmux21IS
PORT（s1,s0:
INSTD_LOGIC_VECTOR;
a,b,c,d:
INSTD_LOGIC;
y:
OUTSTD_LOGIC）;
ENDENTITYmux21;
ARCHITECTUREtwoOFmux21IS
SIGNALs:
STD_LOGIC_VECTOR（1DOWNTO0）;
BEGIN
s<=s1&s0;
PROCESS（s）
BEGIN
CASEsIS
WHEN“00”=>y<=a;
WHEN“01”=>y<=b;
WHEN“10”=>y<=c;
WHEN“11”=>y<=d;
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
ENDARCHITECTUREtwo;
3-3程序：
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYMUXKIS
PORT（s0,s1:
INSTD_LOGIC;
a1,a2,a3:
INSTD_LOGIC;
outy:
OUTSTD_LOGIC）;
ENDENTITYMUXK;
ARCHITECTUREdoubleOFMUXKIS
SIGNALtmp:
STD_LOGIC;--内部连接线
BEGIN
p_MUX21A_u1:
PROCESS（u1_s,u1_a,u1_b,u1_y）
SIGNALu1_s,u1_a,u1_b,u1_y:
STD_LOGIC;
BEGIN
IFu1_s=’0’THENu1_y<=u1_a;
ELSIFu1_y<=u1_b;
ELSEu1_y<=NULL;
ENDIF;
ENDPROCESSp_MUX21A_u1;
p_MUX21A_u2:
PROCESS（u2_s,u2_a,u2_b,u2_y）
SIGNALu2_s,u2_a,u2_b,u2_y:
STD_LOGIC;
BEGIN
IFu2_s=’0’THENu2_y<=u2_a;
ELSIFu2_y<=u2_b;
ELSEu2_y<=NULL;
ENDIF;
ENDPROCESSp_MUX21A_u2;
u1_s<=s0;u1_a<=a2;u1_b<=a3;
tmp<=u1_y;
u2_s<=s1;u2_a<=a1;u2_b<=tmp;
outy<=u2_y;
ENDARCHITECTUREdouble;
3-4程序：
（1）1位半减器
1位半减器的设计选用
（2）图，两种表达方式：
一、LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYh_suberIS
PORT（x,y:
INSTD_LOGIC;
s_out,diff:
OUTSTD_LOGIC）;
ENDENTITYh_suber;
ARCHITECTUREfhd1OFh_suberIS
BEGIN
diff<=xXORy;s_out<=（NOTa）ANDb;
ENDARCHITECTUREfhd1;
二、LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYh_suberIS
PORT（x,y:
INSTD_LOGIC;
s_out,diff:
OUTSTD_LOGIC）;
ENDENTITYh_suber;
ARCHITECTUREfhd1OFh_suberIS
SIGNALs:
STD_LOGIC_VECTOR（1DOWNTO0）;
BEGIN
s<=x&y;
PROCESS（s）
BEGIN
CASEsIS
WHEN“00”=>s_out<=’0’;diff<=’0’;
WHEN“01”=>s_out<=’1’;diff<=’1’;
WHEN“10”=>s_out<=’0’;diff<=’1’;
WHEN“11”=>s_out<=’0’;diff<=’0’;
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
ENDARCHITECTUREfhd1;
或门逻辑描述：
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYorIS
PORT（a,b:
INSTD_LOGIC;
c:
OUTSTD_LOGIC）;
ENDENTITYor;
ARCHITECTUREoneOForIS
BEGIN
c<=aORb;
ENDARCHITECTUREone;
1位全减器：
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYf_suberIS
PORT（x,y,sub_in:
INSTD_LOGIC;
sub_out,diffr:
OUTSTD_LOGIC）;
ENDENTITYf_suber;
ARCHITECTUREfhd1OFf_suberIS
COMPONENTh_suberIS
PORT（x,y:
INSTD_LOGIC;
s_out,diff:
OUTSTD_LOGIC）;
ENDCOMPONENTh_suber;
COMPONENTorIS
PORT（a,b:
INSTD_LOGIC;
c:
OUTSTD_LOGIC）;
ENDCOMPONENTor;
SIGNALd,e,f:
STD_LOGIC;
BEGIN
u1:
h_suberPORTMAP（x=>x,y=>y,diff=>d,s_out=>e）;
u2:
h_suberPORTMAP（x=>d,y=>sub_in,diff=>diffr,s_out=>f）;
u3:
orPORTMAP（a=>f,b=>e,c=>sub_out）;
ENDARCHITECTUREfhd1;
（2）8位减法器：
f_suber
sub_inxy
sub_out
diffr
0
x
0
y
0
f_suber
sub_inxy
sub_out
diffr
1
x
1
y
1
f_suber
sub_inxy
sub_out
diffr
2
x
2
y
2
f_suber
sub_inxy
sub_out
diffr
3
x
3
y
3
f_suber
sub_inxy
sub_out
diffr
4
x
4
y
4
f_suber
sub_inxy
sub_out
diffr
5
x
5
y
5
f_suber
sub_inxy
sub_out
diffr
6
x
6
y
6
f_suber
sub_inxy
sub_out
diffr
7
x
7
y
7
sub_out
abc
d
efg
u0u1u2u3
u4u5u6u7
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITY8f_suberIS
PORT（x0,x1,x2,x3,x4,x5,x6,x7:
INSTD_LOGIC;
y0,y1,y2,y3,y4,y5,y6,y7:
INSTD_LOGIC;
sub_in:
INSTD_LOGIC;
sub_out:
OUTSTD_LOGIC;
diffr0,diffr1,diffr2,diffr3:
OUTSTD_LOGIC;
diffr4,diffr5,diffr6,diffr7:
OUTSTD_LOGIC）;
ENDENTITY8f_suber;
ARCHITECTURE8fhd1OF8f_suberIS
COMPONENTf_suberIS
PORT（x,y,sub_in:
INSTD_LOGIC;
sub_out,diffr:
OUTSTD_LOGIC）;
ENDCOMPONENTf_suber;
SIGNALa,b,c,d,e,f,g:
STD_LOGIC;
BEGIN
u0:
f_suberPORTMAP（x=>x0,y=>y0,sub_in=>,sub_out=>a,
diff=>diff0）;
u1:
f_suberPORTMAP（x=>x1,y=>y1,sub_in=>a,sub_out=>b,
diff=>diff1）;
u2:
f_suberPORTMAP（x=>x2,y=>y2,sub_in=>b,sub_out=>c,
diff=>diff2）;
u3:
f_suberPORTMAP（x=>x3,y=>y3,sub_in=>c,sub_out=>d,
diff=>diff3）;
u4:
f_suberPORTMAP（x=>x4,y=>y4,sub_in=>d,sub_out=>e,
diff=>diff4）;
u5:
f_suberPORTMAP（x=>x5,y=>y5,sub_in=>e,sub_out=>f,
diff=>diff5）;
u6:
f_suberPORTMAP（x=>x6,y=>y6,sub_in=>f,sub_out=>g,
diff=>diff6）;
u7:
f_suberPORTMAP（x=>x7,y=>y7,sub_in=>g,sub_out=>
sub_out,diff=>diff7）;
ENDARCHITECTURE8fhd1;
3-5程序：
或非门逻辑描述：
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYnorIS
PORT（d,e:
INSTD_LOGIC;
f:
OUTSTD_LOGIC）;
ENDENTITYnor;
ARCHITECTUREoneOFnorIS
BEGIN
f<=NOT（dORe）;
ENDARCHITECTUREone;
时序电路描述：
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYcircuitIS
PORT（CL,CLK0:
INSTD_LOGIC;
OUT1:
OUTSTD_LOGIC）;
ENDENTITYcircuit;
ARCHITECTUREoneOFcircuitIS
COMPONENTDFF1IS
PORT（CLK:
INSTD_LOGIC;
D:
INSTD_LOGIC;
Q:
OUTSTD_LOGIC）;
ENDCOMPONENTDFF1;
COMPONENTnorIS
PORT（d,e:
INSTD_LOGIC;
f:
OUTSTD_LOGIC）;
ENDCOMPONENTnor;
COMPONENTnotIS
PORT（g:
INSTD_LOGIC;
h:
OUTSTD_LOGIC）;
ENDCOMPONENTnot;
SIGNALa,b,c:
STD_LOGIC;
BEGIN
u0:
norPORTMAP（d=>c,e=>CL,f=>a）;
u1:
DFF1PORTMAP（CLK=>CLK0,D=>a,Q=>b）;
u2:
notPORTMAP（g=>b,g=>c,h=>OUT1）;
ENDARCHITECTUREone;
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
程序1：
SIGNALA,EN:
STD_LOGIC;
PROCESS（A,EN）
VARIABLEB:
STD_LOGIC;
BEGIN
IFEN=‘1’THENB:
=A;
ENDIF;
ENDPROCESS;
程序2：
ARCHITECTUREoneOFsampleIS
VARIABLEa,b,c:
BEGIN
c:
=a+b;
ENDARCHITECTUREone;
程序3：
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmux21IS
PORT（a,b:
INSTD_LOGIC;
sel:
INSTD_LOGIC;
c:
OUTSTD_LOGIC）;
ENDENTITYmux21;
ARCHITECTUREoneOFmux21IS
BEGIN
IFsel=‘0’THENc<=a;
ELSEc<=b;
ENDIF;
ENDARCHITECTUREone;
第4章QuartusII使用方法
习题
4-1
第5章VHDL状态机
习题
5-1例5-4（两个进程）：
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYMOORE1IS
PORT（DATAIN:
INSTD_LOGIC_VECTOR（1DOWNTO0）;
CLK,RST:
INSTD_LOGIC;
Q:
OUTSTD_LOGIC_VECTOR（3DOWNTO0））;
ENDENTITYMOORE1;
ARCHITECTUREbehavOFMOORE1IS
TYPEST_TYPEIS（ST0,ST1,ST2,ST3,ST4）;
SIGNALC_ST,N_ST:
ST_TYPE;
BEGIN
REG:
PROCESS（RST,CLK）
BEGIN
IFRST=’1’THENC_ST<=ST0;Q<=”0000”;
ELSIFCLK’EVENTANDCLK=’1’THEN
C_ST<=N_ST;
ENDIF;
ENDPROCESS;
COM:
PROCESS（C_ST,DATAIN）
BEGIN
CASEC_STIS
WHENST0=>
IFDATAIN=“10”THENN_ST<=ST1;
ELSEN_ST<=ST0;
ENDIF;
Q<=”1001”;
WHENST1=>
IFDATAIN=“11”THENN_ST<=ST2;
ELSEN_ST<=ST1;
ENDIF;
Q<=”0101”;
WHENST2=>
IFDATAIN=“01”THENN_ST<=ST3;
ELSEN_ST<=ST0;
ENDIF;
Q<=”1100”;
WHENST3=>
IFDATAIN=“00”THENN_ST<=ST4;
ELSEN_ST<=ST2;
ENDIF;
Q<=”0010”;
WHENST4=>
IFDATAIN=“11”THENN_ST<=ST0;
ELSEN_ST<=ST3;
ENDIF;
Q<=”1001”;
WHENOTHERS=>N_ST<=ST0;
ENDCASE;
ENDPROCESS;
ENDARCHITECTUREbehav;
5-2例5-5（单进程）：
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYMEALY1IS
PORT（CLK,DATAIN,RESET:
INSTD_LOGIC;
Q:
OUTSTD_LOGIC_VECTOR（4DOWNTO0））;
ENDENTITYMEALY1;
ARCHITECTUREbehavOFMEALY1IS
TYPEstatesIS（st0,st1,st2,st3,st4）;
SIGNALSTX:
states;
BEGIN
PROCESS（CLK,RESET）
BEGIN
IFRESET=‘1’THENSTX<=st0;
ELSIFCLK’EVENTANDCLK=‘1’THEN
CASESTXIS
WHENst0=>
IFDATAIN=‘1’THENSTX<=st1;Q<=”10000”;
ELSEQ<=”01010”;
ENDIF;
WHENst1=>
IFDATAIN=‘0’THENSTX<=st2;Q<=”10111”;
ELSEQ<=”10100”;
ENDIF;
WHENst2=>
IFDATAIN=‘1’THENSTX<=st3;Q<=”10101”;
ELSEQ<=”10011”;
ENDIF;
WHENst3=>
IFDATAIN=‘0’THENSTX<=st4;Q<=”11011”;
ELSEQ<=”01001”;
ENDIF;
WHENst4=>
IFDATAIN=‘1’THENSTX<=st0;Q<=”11101”;
ELSEQ<=”01101”;
ENDIF;
WHENOTHERS=>STX<=st0;Q<=”00000”;
ENDCASE;
ENDPROCESS;
ENDARCHITECTUREbehav;
5-3序列检测器：
要求1：
要求2：
要求3：
5-4
5-5
第6章16位CISCCPU设计
习题
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
第7章VHDL语句
习题
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
第8章VHDL结构
习题
8-1
8-2
8-3
8-4
8-5VHDL综合器支持的类型：
STRING、BIT；
8-6【例8-28】
LIBRARYIEEE;--
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYdecoder3t08IS
port（input:
INSTD_LOGIC_VECTOR（2DOWNTO0）;
output:
OUTBIT_VECTOR（7DOWNTO0））;
ENDENTITYdecoder3t08;
ARCHITECTUREbehaveOFdecoder3t08IS
BEGIN
output<=“”SLLCONV_INTEGER（input）;
inputoutput
000
001
010
011
100
101
110
111
ENDbehave;
8-7不能，因为求和操作符的操作数的数
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