基于FPGA数字秒表设计.docx
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基于FPGA数字秒表设计
1.秒表设计要求
(1)秒表的计时范围为00:
00:
00~59:
59:
99。
(2)两个按钮开关Start/Stop和Split/Reset,控制秒表的启动、停止、分段和复位:
在秒表已经被复位的情况下,按下“Start/Stop”键,秒表开始计时。
在秒表正常运行的情况下,如果按下“Start/Stop”键,则秒表暂停计时;再次按下该键,秒表继续计时。
在秒表正常运行的情况下,如果按下“Split/Reset”键,显示停止在按键时的时间,但秒表仍然在计时;再次按下该键,秒表恢复正常显示。
在秒表暂停计时的情况下,按下“Split/Reset”键,秒表复位归零。
2.设计思路
2.1功能模块
2.1.1分频器
对晶体振荡器产生的时钟信号进行分频,产生时间基准信号
2.1.2计数器
对时间基准脉冲进行计数,完成计时功能
2.1.3数据锁存器
锁存数据使显示保持暂停
2.1.4控制器
通过产生锁存器的使能信号来控制计数器的运行、停止以及复位
设计分析:
2.1.5扫描显示的控制电路
包括扫描计数器、数据选择器和7段译码器,控制8个数码管以扫描方式显示计时结果,原理图如下:
2.1.6显示电路
2.1.7按键消抖电路
消除按键输入信号抖动的影响,输出单脉冲
按键按下时,FPGA的输入为低电平;松开按键时,FPGA的输入为高电平
但是在按下按键和松开按键的瞬间会出现抖动现象
2.2电路框图
3.电路实现
----------------------------------------------------------------------------------
--Company:
--Engineer:
--
--CreateDate:
09:
08:
3903/12/2011
--DesignName:
--ModuleName:
stopwatch_1-Behavioral
--ProjectName:
--TargetDevices:
--Toolversions:
--Description:
--
--Dependencies:
--
--Revision:
--Revision0.01-FileCreated
--AdditionalComments:
--
----------------------------------------------------------------------------------
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
----Uncommentthefollowinglibrarydeclarationifinstantiating
----anyXilinxprimitivesinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;
entitystopwatch_1is
Port(
Clk:
inSTD_LOGIC;
start_stop:
inSTD_LOGIC;
split_reset:
inSTD_LOGIC;
ncs:
outSTD_LOGIC;
s:
outSTD_LOGIC_VECTOR(2downto0);
seg:
outSTD_LOGIC_VECTOR(7downto0)
);
endstopwatch_1;
architectureBehavioralofstopwatch_1is
signalk1,k2,k3,k4:
STD_LOGIC;
signalcnt_1,cnt_2:
STD_LOGIC_VECTOR(1downto0);
signalstart_stop_out,split_reset_out:
STD_LOGIC;
signalcount:
STD_LOGIC_VECTOR(15downto0):
=(others=>'0');
signalclk_1k:
STD_LOGIC;
signalz0,z1,z2,z3,z4,z5,z6,q1,q2,q3,q4,q5,q6:
STD_LOGIC_VECTOR(3downto0):
=(others=>'0');
signalcount_2:
STD_LOGIC_VECTOR(2downto0):
=(others=>'0');
signalin_7:
STD_LOGIC_VECTOR(3downto0);
signalsreg:
STD_LOGIC_VECTOR(2downto0):
="111";
signalsnext:
STD_LOGIC_VECTOR(2downto0);
Begin
---------------------------------------------------------为三八译码器置入使能信号
ncs<='0';
---------------------------------------------------------分频电路
process(clk)
begin
ifrising_edge(clk)then
ifcount=47999then
count<=(others=>'0');
else
count<=count+1;
endif;
endif;
endprocess;
clk_1k<=count(15);
---------------------------------------------------------同步计数电路
process(clk_1k,sreg
(2))
begin
ifrising_edge(clk_1k)then
ifsreg
(2)='1'then
z0<=(others=>'0');
z1<=(others=>'0');
z2<=(others=>'0');
z3<=(others=>'0');
z4<=(others=>'0');
z5<=(others=>'0');
z6<=(others=>'0');
elsifsreg
(1)='1'then
z0<=z0+1;
ifz0=9then
z0<=(others=>'0');
z1<=z1+1;
ifz1=9then
z1<=(others=>'0');
z2<=z2+1;
ifz2=9then
z2<=(others=>'0');
z3<=z3+1;
ifz3=9then
z3<=(others=>'0');
z4<=z4+1;
ifz4=5then
z4<=(others=>'0');
z5<=z5+1;
ifz5=9then
z5<=(others=>'0');
z6<=z6+1;
ifz6=5then
z6<=(others=>'0');
endif;
endif;
endif;
endif;
endif;
endif;
endif;
endif;
endif;
endprocess;
---------------------------------------------------------扫描计数器
process(clk_1k)
begin
ifrising_edge(clk_1k)then
count_2<=count_2+1;
endif;
endprocess;
s<=count_2;
---------------------------------------------------------锁存器
process(sreg(0),z1,z2,z3,z4,z5,z6)
begin
ifsreg(0)='1'then
q1<=z1;
q2<=z2;
q3<=z3;
q4<=z4;
q5<=z5;
q6<=z6;
endif;
endprocess;
---------------------------------------------------------
process(count_2,q1,q2,q3,q4,q5,q6)
begin
casecount_2is
when"000"=>in_7<=q1;
when"001"=>in_7<=q2;
when"011"=>in_7<=q3;
when"100"=>in_7<=q4;
when"110"=>in_7<=q5;
when"111"=>in_7<=q6;
whenothers=>in_7<="1111";
endcase;
endprocess;
---------------------------------------------------------八段译码器
process(in_7)
begin
casein_7is
when"0000"=>seg<="00000011";
when"0001"=>seg<="10011111";
when"0010"=>seg<="00100101";
when"0011"=>seg<="00001101";
when"0100"=>seg<="10011001";
when"0101"=>seg<="01001001";
when"0110"=>seg<="01000001";
when"0111"=>seg<="00011111";
when"1000"=>seg<="00000001";
when"1001"=>seg<="00001001";
whenothers=>seg<="11111101";
endcase;
endprocess;
---------------------------------------------------------按键去抖电路
process(clk_1k,start_stop)
begin
ifclk_1k'eventandclk_1k='0'then
ifcnt_1=3then
k1<='1';
else
k1<='0';
cnt_1<=cnt_1+1;
endif;
k2<=k1;
endif;
ifstart_stop='0'then
cnt_1<="00";
endif;
endprocess;
start_stop_out<=notk1andk2;
process(clk_1k,split_reset)
begin
ifclk_1k'eventandclk_1k='0'then
ifcnt_2=3then
k3<='1';
else
k3<='0';
cnt_2<=cnt_2+1;
endif;
k4<=k3;
endif;
ifsplit_reset='0'then
cnt_2<="00";
endif;
endprocess;
split_reset_out<=notk3andk4;
---------------------------------------------------------控制器
process(clk_1k,start_stop_out,split_reset_out)
begin
ifrising_edge(clk_1k)then
sreg<=snext;
endif;
endprocess;
process(start_stop_out,split_reset_out,sreg)
begin
casesregis
when"111"=>ifstart_stop_out='1'andsplit_reset_out='0'thensnext<="011";
elsesnext<=sreg;
endif;
when"011"=>ifstart_stop_out='1'andsplit_reset_out='0'thensnext<="001";
elsifstart_stop_out='0'andsplit_reset_out='1'thensnext<="010";
elsesnext<=sreg;
endif;
when"001"=>ifstart_stop_out='0'andsplit_reset_out='1'thensnext<="111";
elsifstart_stop_out='1'andsplit_reset_out='0'thensnext<="011";
elsesnext<=sreg;
endif;
when"010"=>ifstart_stop_out='0'andsplit_reset_out='1'thensnext<="011";
elsesnext<=sreg;
endif;
whenothers=>snext<="111";
endcase;
endprocess;
endBehavioral;
注:
控制器设计时,巧妙地将状态编码和控制器输出的控制信号编码合二为一,即状态编码也是控制信号编码,使得程序形式上更为简单、清晰。
4.程序仿真
4.1分频器
entityfpis
Port(clk_48M:
inSTD_LOGIC;
clk_1k:
outSTD_LOGIC);
endfp;
architectureBehavioraloffpis
signalcount:
STD_LOGIC_VECTOR(15downto0):
=(others=>'0');
begin
process(clk_48M)
begin
ifrising_edge(clk_48M)then
ifcount=47999then
count<=(others=>'0');
else
count<=count+1;
endif;
endif;
endprocess;
clk_1k<=count(15);
endBehavioral;
tb:
PROCESS
BEGIN
clk_48M<='1';waitfor10.4ns;
clk_48M<='0';waitfor10.4ns;
ENDPROCESS;
4.1.1计数器电路综合
4.1.2计数器电路仿真
由图可得分频后的信号周期T=999333718ps≈0.001s即的到了1KHz的信号
由图可得时钟信号周期T=20845ps≈20.845ns即的到了48MHz的时钟信号
4.2同步计数器
4.2.1计数器实现
entitycount_6is
Port(clk_1k:
inSTD_LOGIC;
d1:
outSTD_LOGIC_VECTOR(3downto0);
d2:
outSTD_LOGIC_VECTOR(3downto0);
d3:
outSTD_LOGIC_VECTOR(3downto0);
d4:
outSTD_LOGIC_VECTOR(3downto0);
d5:
outSTD_LOGIC_VECTOR(3downto0);
d6:
outSTD_LOGIC_VECTOR(3downto0));
endcount_6;
architectureBehavioralofcount_6is
signalz0,z1,z2,z3,z4,z5,z6:
STD_LOGIC_VECTOR(3downto0):
=(others=>'0');
signalclr,en:
STD_LOGIC;
Begin
clr<='0';---------------------------------------------清零无效
en<='1';---------------------------------------------计数使能有效
d1<=z1;
d2<=z2;
d3<=z3;
d4<=z4;
d5<=z5;
d6<=z6;
process(clk_1k,clr)
begin
ifrising_edge(clk_1k)then
ifclr='1'then
z0<=(others=>'0');
z1<=(others=>'0');
z2<=(others=>'0');
z3<=(others=>'0');
z4<=(others=>'0');
z5<=(others=>'0');
z6<=(others=>'0');
elsifen='1'then
z0<=z0+1;
ifz0=9then
z0<=(others=>'0');
z1<=z1+1;
ifz1=9then
z1<=(others=>'0');
z2<=z2+1;
ifz2=9then
z2<=(others=>'0');
z3<=z3+1;
ifz3=9then
z3<=(others=>'0');
z4<=z4+1;
ifz4=5then
z4<=(others=>'0');
z5<=z5+1;
ifz5=9then
z5<=(others=>'0');
z6<=z6+1;
ifz6=5then
z6<=(others=>'0');
endif;
endif;
endif;
endif;
endif;
endif;
endif;
endif;
endif;
endprocess;
endBehavioral;
4.2.2计数器仿真
tb:
PROCESS
BEGIN
clk_1k<='0';waitfor0.5ms;
clk_1k<='1';waitfor0.5ms;
ENDPROCESS;
0.01s位
由图可以看出为十进制
0.1s位
由图可以看出为十进制
1s位
由图可以看出为十进制
10s位
由图可以看出为六进制
1min位
由图可以看出为十进制
10min位
由图可以看出为六进制
4.2.3同步计数器电路综合
4.3按键消抖电路
4.3.1按键消抖电路实现
entityquedouis
Port(clk_1k:
inSTD_LOGIC;
key_in:
inSTD_LOGIC;
key_out:
outSTD_LOGIC);
endquedou;
architectureBehavioralofquedouis
signalk1,k2:
STD_LOGIC;
signalcnt_1:
STD_LOGIC_VECTOR(1downto0);
begin
process(clk_1k,key_in)
begin
ifclk_1k'eventandclk_1k='0'then
ifcnt_1=3then
k1<='1';
else
k1<='0';
cnt_1<=cnt_1+1;
endif;
k2<=k1;
endif;
ifkey_in='0'then
c