EDA课后答案适用于《EDA技术及应用》.docx
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EDA课后答案适用于《EDA技术及应用》
1.1、设计集成计数器74161，设计要求如下：
4-BitBinaryUpCounterwithSynchronousLoadandAsynchronousClearNote
Inputs：
CLKLDNCLRNDCBA
Outputs：
QDQCQBQARCO
*RCO=QD&QC&QB&QA
Libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycnt4is
port（
clk,LDN,CLRN:
instd_logic;
d,c,b,a:
instd_logic;
carry:
outstd_logic;
qd,qc,qb,qa:
outstd_logic
）;
end;
architectureaofcnt4is
signaldata_in:
std_logic_vector（3downto0）;
begin
data_in<=d&c&b&a;
process（data_in,clk,ldn,clrn）
variablecnt:
std_logic_vector（3downto0）;
begin
ifclrn='0'then
cnt:
=（others=>'0'）;
elsifclk'eventandclk='1'then
ifldn='0'then
cnt:
=data_in;
else
cnt:
=cnt+1;
endif;
endif;
casecntis
when"1111"=>carry<='1';
whenothers=>carry<='0';
endcase;
qa<=cnt（0）;
qb<=cnt
（1）;
qc<=cnt
（2）;
qd<=cnt（3）;
endprocess;
enda;
1.2、设计一个通用双向数据缓冲器，要求缓冲器的输入和输出端口的位数可以由参数决定。
设计要求：
nbit数据输入端口a，b。
工作使能端口en=0时双向总线缓冲器选通，
Dir=1，则a=b；反之b=a。
Libraryieee;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYbidirIS
generic（n:
integer:
=8）;
PORT（a,b:
INOUTSTD_LOGIC_VECTOR（n-1DOWNTO0）;
en,dir:
INSTD_LOGIC）;
END;
ARCHITECTUREaOFbidirIS
BEGIN
PROCESS（en,dir）
BEGIN
ifen='0'then
a<=（OTHERS=>'Z'）;
b<=（OTHERS=>'Z'）;
else
ifdir='1'then
b<=a;
else
a<=b;
endif;
endif;
ENDPROCESS;
ENDa;
2.1、用VHDL语言编程实现十进制计数器，要求该计数器具有异步复位、同步预置功能。
libraryieee;
useieee.std_logic_1164.all;
entitycnt_10_2is
port（
clk,clr:
instd_logic;
count:
outstd_logic
）;
end;
architectureaofcnt_10_2is
signalcnt_10:
integerrange0to10;
begin
process（clk,clr）
begin
ifclr='1'then
cnt_10<=0;
elsifclk'eventandclk='1'then
cnt_10<=cnt_10+1;
ifcnt_10=9then
cnt_10<=0;
count<='1';
else
count<='0';
endif;
endif;
endprocess;
enda;
2.2、设计实现一位全减器。
行为描述:
f_sub4
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityf_sub4is
port（
a,b,cin:
INstd_logic;
diff,Cout:
OUTstd_logic
）;
end;
architectureaoff_sub4is
begin
diff<=axorbxorcin;
cout<=（notaandb）or（notaandcin）or（bandcin）;
enda;
数据流描述f_sub1
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityf_sub1is
port（
a,b:
INstd_logic;
cin:
INstd_logic;
diff,Cout:
OUTstd_logic
）;
end;
architectureaoff_sub1is
signals:
std_logic_vector（2downto0）;
begin
s<=Cin&a&b;
process（a,b,cin）
begin
casesis
when"000"=>diff<='0';cout<='0';
when"001"=>diff<='1';cout<='1';
when"010"=>diff<='1';cout<='0';
when"011"=>diff<='0';cout<='0';
when"100"=>diff<='1';cout<='1';
when"101"=>diff<='0';cout<='1';
when"110"=>diff<='0';cout<='0';
when"111"=>diff<='1';cout<='1';
whenothers=>diff<='X';cout<='X';
endcase;
endprocess;
enda;
数据流描述f_sub2
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityf_sub2is
port（
a,b,cin:
INstd_logic;
diff,Cout:
OUTstd_logic
）;
end;
architectureaoff_sub2is
signals:
std_logic_vector（2downto0）;
signalc:
std_logic_vector（1downto0）;
begin
s<=Cin&a&b;
diff<=c
（1）;
cout<=c（0）;
c<="00"whens="000"else
"11"whens="001"else
"10"whens="010"else
"00"whens="011"else
"11"whens="100"else
"01"whens="101"else
"00"whens="110"else
"11";
enda;
数据流描述f_sub3
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityf_sub3is
port（
a,b,cin:
INstd_logic;
diff,Cout:
OUTstd_logic
）;
end;
architectureaoff_sub3is
signals:
std_logic_vector（2downto0）;
signalc:
std_logic_vector（1downto0）;
begin
s<=Cin&a&b;
diff<=c
（1）;
cout<=c（0）;
withsselect
c<="00"when"000",
"11"when"001",
"10"when"010",
"00"when"011",
"11"when"100",
"01"when"101",
"00"when"110",
"11"whenothers;
enda;
3.1、阅读教材P181页，例[5-55]并回答下列问题：
（1）、该程序的功能是什么？
（2）、请写出该程序所有端口的功能描述。
3.2、试描述一个十进制——BCD码编码器，输出使能为低电平有效。
libraryieee;
useieee.std_logic_1164.all;
entitybin_bcdis
port（
bin:
inintegerrange0to20;
--ena:
instd_logic;
BCD_out:
outstd_logic_vector（7downto0）
）;
end;
architectureaofbin_bcdis
begin
Binary_BCD:
Block
BEGIN
BCD_out<="00000000"WHENBIN=0ELSE
"00000001"WHENBIN=1ELSE
"00000010"WHENBIN=2ELSE
"00000011"WHENBIN=3ELSE
"00000100"WHENBIN=4ELSE
"00000101"WHENBIN=5ELSE
"00000110"WHENBIN=6ELSE
"00000111"WHENBIN=7ELSE
"00001000"WHENBIN=8ELSE
"00001001"WHENBIN=9ELSE
"00010000"WHENBIN=10ELSE
"00010001"WHENBIN=11ELSE
"00010010"WHENBIN=12ELSE
"00010011"WHENBIN=13ELSE
"00010100"WHENBIN=14ELSE
"00010101"WHENBIN=15ELSE
"00010110"WHENBIN=16ELSE
"00010111"WHENBIN=17ELSE
"00011000"WHENBIN=18ELSE
"00011001"WHENBIN=19ELSE
"00100000"WHENBIN=20ELSE
"00000000";
endblock;
enda;
4.1、读教材P151页，例[5-32]的程序，并回答以下问题：
（1）请画出该程序所描述的电路结构图，要求标清楚每一个端口以及内部信号。
（串入/串出移位寄存器）
4.2、用VHDL语言设计一个能够实现任意整数进制的计数器。
libraryieee;
useieee.std_logic_1164.all;
--**********************************************
entityfreqdv_Nis
generic（N:
integer:
=6）;
port（
clk:
instd_logic;
clk_div:
outstd_logic
）;
end;
architectureaoffreqdv_Nis
signalcnt:
integerrange0toN;
begin
process（clk）
begin
ifrising_edge（clk）then
ifcnt=0then
cnt<=N-1;
clk_div<='1';
else
clk_div<='0';
cnt<=cnt-1;
endif;
endif;
endprocess;
enda;
5.1、设计一个序列信号发生器，要求能够循环输出序列“01101001”。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityRS_1is
port（
cp,s,R:
INstd_logic;
q,nq:
outstd_logic
）;
end;
architectureaofrs_1is
signals1,r1,q1,nq1:
std_logic;
begin
s1<=snandcp;
r1<=rnandcp;
q1<=s1nandnq1;
nq1<=r1nandq1;
q<=q1;
nq<=nq1;
enda;
5.2、设计一个带复位端、置位端、CP下降沿触发的JK触发器。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityjkffis
port（
j,k,rst,clr:
INbit;
clk:
inbit;
q,nq:
outbit
）;
end;
architectureaofjkffis
signalq_s,nq_s:
bit;
begin
process（j,k,rst,clr,clk）
begin
ifrst='1'then
q_s<='1';
nq_s<='0';
elsifclk'eventandclk='0'then
ifclr='1'then
q_s<='0';
nq_s<='1';
elsifj='0'andk='1'then
q_s<='0';
nq_s<='1';
elsifj='1'andk='0'then
q_s<='1';
nq_s<='0';
elsifj='1'andk='1'then
q_s<=notq_s;
nq_s<=notnq_s;
endif;
else
null;
endif;
q<=q_s;
nq<=nq_s;
endprocess;
enda;
6.1、用VHDL语句描述一个三态输出的双4选一的数据选择器，其地址信号共用，且各有一个低电平有效的使能端。
libraryieee;
useieee.std_logic_1164.all;
entitydual_mux_41is
port（
a,b,c,d:
instd_logic;
ena_n,enb_n:
instd_logic;
s:
instd_logic_vector（1downto0）;
outa,outb:
outstd_logic
）;
end;
architectureaofdual_mux_41is
signalp,q:
std_logic_vector（2downto0）;
begin
p<=ena_n&s;
q<=enb_n&s;
withpselect
outa<=awhen"000",
bwhen"001",
cwhen"010",
dwhen"011",
'Z'whenothers;
withqselect
outb<=awhen"000",
bwhen"001",
cwhen"010",
dwhen"011",
'Z'whenothers;
enda;
6.2、用并行信号赋值语句实现3—8译码器。
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYdecoder38IS
PORT（a,b,c,g1,g1a,a2b:
INSTD_LOGIC;
q:
OUTSTD_LOGIC_VECTOR（7DOWNTO0））;
ENDdecoder38;
ARCHITECTUREbehave38OFdecoder38IS
SIGNALinda:
STD_LOGIC_VECTOR（2DOWNTO0）;
BEGIN
inda<=c&b&a;
PROCESS（indata,g1,g2a,g2b）
BEGIN
IF（g1='1'ANDg2a='0'ANDg2b='0'）THEN
CASEindaIS
WHEN"000"=>q<="11111110";
WHEN"001"=>q<="11111101";
WHEN"010"=>q<="11111011";
WHEN"011"=>q<="11110111";
WHEN"100"=>q<="11101111";
WHEN"101"=>q<="11011111";
WHEN"110"=>q<="10111111";
WHEN"111"=>q<="01111111";
WHENOTHERS=>q<="XXXXXXXX";
ENDCASE;
ELSE
q<="11111111";
ENDIF;
ENDPROCESS;
ENDbehave38;
7.1、用并行信号赋值语句实现8选一数据选择器，要求有工作使能端。
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmux8IS
PORT（d0,d1,d2,d3,d4,d5,d6,d7:
INSTD_LOGIC_VECTOR（7DOWNTO0）;
s0,s1,s2:
INSTD_LOGIC;
q:
OUTSTD_LOGIC_VECTOR（7DOWNTO0））;
ENDmux8;
ARCHITECTUREbehaveOFmux8IS
SIGNALs:
STD_LOGIC_VECTOR（2DOWNTO0）;
BEGIN
s<=s2&s1&s0;
WITHsSECLECT
d<=d0WHEN"000",
d1WHEN"001",
d2WHEN"010",
d3WHEN"011",
d4WHEN"100",
d5WHEN"101",
d6WHEN"110",
d7WHEN"111",
‘X’WHENOTHERS;
ENDbehave;
7.2、用VHDL语言设计实现输出占空比为50%的1000分频器。
libraryieee;
useieee.std_logic_1164.all;
entitydiv_1000is
port（
clk,clr:
instd_logic;
div:
outstd_logic
）;
end;
architectureaofdiv_1000is
signalq:
std_logic;
begin
div<=q;
process（clk,clr）
variablecnt:
integerrange0to499;
begin
ifclr='1'then
cnt:
=0;q<='0';
elsifrising_edge（clk）then
ifcnt=499then
cnt:
=0;
q<=notq;
else
cnt:
=cnt+1;
endif;
endif;
endprocess;
enda;
8.1、设计一个一位全减器。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityf_sub3is
port（
a,b,cin:
INstd_logic;
diff,Cout:
OUTstd_logic
）;
end;
architectureaoff_sub3is
signals:
std_logic_vector（2downto0）;
signalc:
std_logic_vector（1downto0）;
begin
s<=Cin&a&b;
diff<=c
（1）;
cout<=c（0）;
withsselect
c<="00"when"000",
"11"when"001",
"10"when"010",
"00"when"011",
"11"when"100",
"01"when"101",
"00"when"110",
"11"whenothers;
enda;
8.2、用元件例化语句描述一个四位的全减器。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityf_sub4_1is
port（
a,b:
INSTD_LOGIC_VECTOR（3DOWNTO0）;
cin:
INstd_logic;
diff:
outSTD_LOGIC_VECTOR（3DOWNTO0）;
Cout:
OUTstd_logic
）;
end;
architectureaoff_sub4_1is
componentf_sub1is
port（
a,b,cin:
INstd_logic;
diff,Cout:
OUTstd_logic
）;
endcomponent;
signalc:
STD_LOGIC_VECTOR（3DOWNTO0）;
begin
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