计算机体系结构与组成原理.docx
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计算机体系结构与组成原理
1.三种映射方式及地址格式的计算
课本4.5Answer：
（1）Linesize=Blocksize=2x16-bit=21words=>Word#=1-bit
（2）Cachesize=4Kx32-bit
=>Numberofsets=4Kx32-bit/2x16-bit/4lines/set=210sets=>Set#=10-bit
（3）LengthofRA=24bits=>Tag=24-10-1=13-bit
Addressmappingformat
TagSet#word#
13-bit
10-bit
1-bit
2.海明码校验
5.8.Answer:
（1）2k-1≥m+k,m=16-bit=>k=5-bit
（2）真值表
BitPosition
Positionnumber
Checkbit
Databit
21
10101
D16
0
20
10100
D15
1
19
10011
D14
0
18
10010
D13
1
17
10001
D12
0
16
10000
C16
15
01111
D11
0
14
01110
D10
0
13
01101
D9
0
12
01100
D8
0
11
01011
D7
0
10
01010
D6
1
9
01001
D5
1
8
01000
C8
7
00111
D4
1
6
00110
D3
0
5
00101
D2
0
4
00100
C4
3
00011
D1
1
2
00010
C2
1
00001
C1
（3）Calculatesoldcheckbits:
C1（1,2,4,5,7,9,11,12,14,16）=1C2（1,3,4,6,7,10,11,13,14）=0
C4（2,3,4,8,9,10,11,15,16）=0C8（5,6,7,8,9,10,11）=0
C16（12,13,14,15,16）=0=>oldcheckbits：
C16C8C4C2C1=00001
（4）SupposedatabitD5ischangedfrom1to0instorage.010********01001
3..Whenfetchesthedata,Re-calculatesnewcheckbit:
C1’（1,2,4,5,7,9,11,12,14,16）=0C2’（1,3,4,6,7,10,11,13,14）=0
C4’（2,3,4,8,9,10,11,15,16）=0C8’（5,6,7,8,9,10,11）=1
C16’（12,13,14,15,16）=0=>oldcheckbits：
C16’C8’C4’C2’C1’=01000
（5）Makessyndrome:
C16C8C4C2C100001old
C16’C8’C4’C2’C1’01000new
=>syndromeword01001
Itmeansposition9iserror,D5iswrong,databitD5ischangedfrom0to1.
4.
5.
3RAID磁盘冗余阵列
RAID2Hamming
RAID3
RAID4independentdisks
RAID5（Block-leveldistributedparity）
Writeb0,meanswriteb0&p（0-3）:
disk0&disk4
Writeb5,meanswriteb5&p（4-7）:
disk1&disk3
RAID6（Dualredundancy）
4中断过程11步以及DMA的特点
Interruptprocessing
0.CPUdoessomethingelse….
1.I/OmoduleissuesaninterruptsignaltoCPU
2.TheCPUfinishesexecutionofthecurrentinstructionbeforerespondingtotheinterrupt
3.TheCPUtests&makessureofaninterrupt,andsendsanacknowledgesignaltomodule（allowsthemoduletoremoveitsinterruptsignal&tosendsinterruptnumbertoCPU）
4.TheCPUsavesinformationofcurrentprogramtostackforresumingit.TheimportantinformationisPSW（runningstatusofcurrentprogram）&PC（theaddressofnextinstruction）
5.TheCPUloadsnewPCvaluewiththeentrylocationofISR（InterruptServiceRoutine）whichrespondstothisinterrupt.TheCPUmustdeterminetheenterlocation（startaddress）ofISRbysomemethodbasedoninterruptnumber.
6.TheCPUbeginstoexecutetheinstructionsofISR.Itsavestheremainder（thecontextofsomeregisters）ofprogram-interruptedontostackforresuming….（e.g.ACcontainsthesumofaddition…..）
7.TheCPUexecutesinstructionsofISRtoprocessinterrupt:
testsstatusofmodule,fetchesdatafromthemodule,storesdatatomemory,….（orfetchesdataformmemory,sendsdatatodevice）.
8.Afterservice,theCPUpreparestoresumetheinterruptedprogram,CPUretrievestheremainderfromstack&restoresthemtoregisters.
9.TheCPUexecutesthelastinstructionRETI（meansreturnfrominterrupt）,theprocessingisrestoringPSWandPCfromstack.
10.TheCPUfetchestheinstructionoftheinterruptedprogrambyPC&resumestheinte
DMA
CPUtellsDMAcontroller:
1.Read/Write（thedirection方向问题）2.Deviceaddress
3.Startingaddressofmemoryblockfordata4Amountofdatatobetransferred
CPUcarriesonwithotherwork
DMAcontrollerdealswithtransfer
DMAcontrollersendsinterruptwhenfinished,letCPUservicesforData
5七种寻址方式
1.ImmediateAddressing，立即数寻址
Instruction
Opcode操作码
Operand操作数
•Operandispartofinstruction
•Operand=addressfield
2.DirectAddressing直接寻址
Instruction
Opcode
操作码
AddressA
Memory
Operand操作数
•Singlememoryaccess
•Operandisstandard
•Limitedaddressspace限制寻址空间
3.IndirectAddressing间接寻址
•Largeaddressspace
•Operandisnormal
•Multiplememoryaccessestofindoperand
4.RegisterAddressing寄存器寻址
•Operandisheldinregisternamedinaddressfiled=>EA=R
•Limitednumberofregisters
•Operandisnormal
•Nomemoryaccess,veryfastexecution
•Verylimitedaddressspace
5.RegisterIndirectAddressing寄存器间接寻址
•OperandisinmemorycellpointedtobycontentsofregisterR=>EA=（R）
•Largeaddressspace
•Onefewermemoryaccessthanindirectaddressing
•Operandisnormal
6.DisplacementAddressing偏移寻址
Relativeaddressing相对寻址
Base-registeraddressing基址寄存器Indexing变址
7.StackAddressing堆栈寻址
Operandis（implicitly）ontopofstack
e.g.ADD;Poptoptwoitemsfromstackandadd
onememoryaccessOperandisnormallargememoryspace
6微操作过程
Showallthemicro-operationsandcontrolsignalsforthefollowinginstruction:
1.ADDAX,X;—ThecontentsofACaddsthecontentsoflocationX,resultisstoredtoAC.
2.MOVAX,[X];
—OperandpointedbythecontentoflocationXismovedtoAX,thatmeans（（X））->AX
—[]meansindirectaddressing.
3.ADDAX,[BX];
—OperandpointedbythecontentofRegisterBXisaddedtoAX,thatmeans（AX）+（（BX））->AX
—[]meansregisterindirectaddressing.
4.JZNEXT1;—If（ZF）=0,thenjumpto（PC）+NEXT1.
5.CALLX;—Callxfunction,savereturnaddressonthetopofstack.
6.RETURN;—FromtopofstackreturntoPC.
Answer：
1.ADDAX,X;
FetchcycleExecutecycle
t1:
（PC）->MARt1:
Ad（MBR）->MAR
t2:
（MAR）--->Memoryt2:
（MAR）->Memory
read--->Memoryread->Memory
t3:
Memory--->MBRt3:
Memory->MBR
t4:
（MBR）->IRt4:
（AX）+（MBR）->AX
（PC）+1->PC
2.MOVAX,[X];
FetchcycleIndirectcycleExecutecycle
t1:
（PC）->MARt1:
Ad（MBR）->MARt1:
（MBR）->MAR
t2:
（MAR）--->Memoryt2:
（MAR）->Memoryt2:
（MAR）->Memory
read--->Memoryread->Memoryread->Memory
t3:
Memory--->MBRt3:
Memory->MBRt3:
Memory->MBR
t4:
（MBR）->IRt4:
（MBR）->AX
（PC）+1->PC
3.ADDAX,[BX];
FetchcycleExecutecycle
t1:
（PC）->MARt1:
（BX）->MAR
t2:
（MAR）--->Memoryt2:
（MAR）->Memory
read--->Memoryread->Memory
t3:
Memory--->MBRt3:
Memory->MBR
t4:
（MBR）->IRt4:
（AX）+（MBR）->AX
（PC）+1->PC
4.JZNEXT1;
FetchcycleExecutecycle
t1:
（PC）->MARt1:
if（ZF）=0
t2:
（MAR）--->Memorythen（PC）+（NEXT1）->PC
read--->Memory
t3:
Memory--->MBR
t4:
（MBR）->IR
（PC）+1->PC
5.CALLX;
—Callxfunction,savereturnaddressonthetopofstack.
FetchcycleExecutecycle
t1:
（PC）->MARt1:
（PC）->MBR
t2:
（MAR）--->Memory（SP）->MAR
read--->Memoryt2:
（MBR）--->Memory
t3:
Memory--->MBR（MAR）-->Memory
t4:
（MBR）->IRwrite--->Memory
（PC）+1->PCt3:
Ad（IR）->PC
（SP）-1->SP
（Note:
SPalwayspointsanemptylocationastopofstack.）
6.RETURN;
—FromtopofstackreturntoPC.
FetchcycleExecutecycle
t1:
（PC）->MARt1:
（SP）+1->SP
t2:
（MAR）--->Memory（SP）+1->MAR
read--->Memoryt2:
（MAR）--->Memory
t3:
Memory--->MBRread--->Memory
t4:
（MBR）->IRt3:
Memory--->MBR
（PC）+1->PCt4:
（MBR）->PC
（Note:
SPalwayspointsanemptylocationastopofstack.）
5’.CALLX;
FetchcycleExecutecycle
t1:
（PC）->MARt1:
（PC）->MBR
t2:
（MAR）--->Memory（SP）-1->SP
read--->Memory（SP）-1->MAR
t3:
Memory--->MBRt2:
（MBR）--->Memory
t4:
（MBR）->IR（MAR）--->Memory
（PC）+1->PCwrite--->Memory
t3:
Ad（IR）--->PC
（Note:
SPalwayspointsafulllocationastopofstack.）
6’.RETURN;
FetchcycleExecutecycle
t1:
（PC）->MARt1:
（SP）->MAR
t2:
（MAR）--->Memoryt2:
（MAR）-->Memory
read--->Memoryread--->Memory
t3:
Memory--->MBRt3:
Memory--->MBR
t4:
（MBR）->IRt4:
（MBR）->PC
（PC）+1->PC（SP）+1->SP
（Note:
SPalwayspointsafulllocationastopofstack.）
7.
Executecycle
t1:
Ad（MBR）->MAR
（AC）--->MBR
t2:
（MBR）--->Memory
（MAR）--->Memory
write--->Memory
Fetchcycle
t1:
（PC）->MAR
t2:
（MAR）--->Memory
read--->Memory
t3:
Memory--->MBR
t4:
（MBR）->IR
（PC）+1->PC
Fetchcycle
t1:
（PC）->MAR
t2:
（MAR）--->Memory
read--->Memory
t3:
Memory--->MBR
t4:
（MBR）->IR
（PC）+1->PC
Executecycle
t1:
（SP）->MAR
（AX）--->MBR
t2:
（MBR）--->Memory
（MAR）--->Memory
write--->Memory
（SP）-1--->SP
8.
9.
Executecycle
t1:
（SP）+1->MAR
（SP）+1--->SP
t2:
（MAR）--->Memory
read--->Memory
t3:
Memory--->（MBR）
t4:
（MBR）--->AX
Fetchcycle
t1:
（PC）->MAR
t2:
（MAR）--->Memory
read--->Memory
t3:
Memory--->MBR
t4:
（MBR）->IR
（PC）+1->PC
7MESI协议
CHAPTER18
Inmulti-processorsystems,MESIprotocolisusedtosolvetheproblemofcachecoherence.
IniatialSnoopy
1）Thisisthecaseof________________.
2）Pleasecompletethisfigure.
3）Withthiscase,pleasefillbestanswersintofollowingtable.
Thestatesinbegin
WhereistheValiddatd?
Actions
Thestatesinend
Initial
snoopy
Initial
snoopy
Inmulti-processorsystems,MESIprotocolisusedtosolvetheproblemofcachecoherence.
I
IniatialSnoopy
4）Thisisthecaseof________writehit__________.
5）Pleasecompletethisfigure.
6）Withthiscase,pleasefillbestanswersintofollowingtable.
Thestatesinbegin
WhereistheValiddatd?
Actions
Thestatesinend
Initial
snoopy
Initial
snoopy
S
S
Cache&memory
Iniatialreaddatafromit’sowncache,thenupdateit，transferainvalidatesignal
M
I
E
I
Cache&memory
Iniatialreaddatafromit’sowncache,thenupdateit
M
I
M
I
Cache
Iniatialreaddatafromit’sowncache,thenupdateit
M
I
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