现代CMOS工艺基本流程.ppt

现代CMOS工艺基本流程.ppt

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1,现代CMOS工艺基本流程,现代CMOS工艺基本流程,2,SiliconSubstrateP+,2um,725um,SiliconEpiLayerP,选择衬底,晶圆的选择掺杂类型（N或P）电阻率（掺杂浓度）晶向100高掺杂（P+）的Si晶圆低掺杂（P）的Si外延层,3,SiliconSubstrateP+,SiliconEpiLayerP,PadOxide,热氧化,热氧化形成一个SiO2薄层，厚度约20nm高温，H2O或O2气氛缓解后续步骤形成的Si3N4对Si衬底造成的应力,4,SiliconSubstrateP+,SiliconEpiLayerP-,SiliconNitride,Si3N4淀积,Si3N4淀积厚度约250nm化学气相淀积（CVD）作为后续CMP的停止层,5,SiliconSubstrateP+,SiliconEpiLayerP-,SiliconNitride,Photoresist,光刻胶成形,光刻胶成形厚度约0.51.0um光刻胶涂敷、曝光和显影用于隔离浅槽的定义,6,SiliconSubstrateP+,SiliconEpiLayerP-,SiliconNitride,Photoresist,Si3N4和SiO2刻蚀,Si3N4和SiO2刻蚀基于氟的反应离子刻蚀（RIE）,7,SiliconSubstrateP+,SiliconEpiLayerP-,SiliconNitride,Photoresist,TransistorActiveAreas,IsolationTrenches,隔离浅槽刻蚀,隔离浅槽刻蚀基于氟的反应离子刻蚀（RIE）定义晶体管有源区,8,SiliconSubstrateP+,SiliconEpiLayerP-,SiliconNitride,TransistorActiveAreas,IsolationTrenches,除去光刻胶,除去光刻胶氧等离子体去胶，把光刻胶成分氧化为气体,9,SiliconSubstrateP+,SiliconEpiLayerP-,SiliconNitride,FuturePMOSTransistor,SiliconDioxide,FutureNMOSTransistor,Nocurrentcanflowthroughhere!

SiO2淀积,SiO2淀积用氧化物填充隔离浅槽厚度约为0.51.0um，和浅槽深度和几何形状有关化学气相淀积（CVD）,10,SiliconSubstrateP+,SiliconEpiLayerP-,SiliconNitride,FuturePMOSTransistor,FutureNMOSTransistor,Nocurrentcanflowthroughhere!

化学机械抛光,化学机械抛光（CMP）CMP除去表面的氧化层到Si3N4层为止,11,SiliconSubstrateP+,SiliconEpiLayerP-,FuturePMOSTransistor,FutureNMOSTransistor,除去Si3N4,除去Si3N4热磷酸（H3PO4）湿法刻蚀，约180,12,TrenchOxide,CrossSection,BareSilicon,平面视图,完成浅槽隔离（STI）,13,SiliconSubstrateP+,SiliconEpiLayerP-,FuturePMOSTransistor,FutureNMOSTransistor,Photoresist,光刻胶成形,光刻胶成形厚度比较厚，用于阻挡离子注入用于N-阱的定义,14,SiliconSubstrateP+,SiliconEpiLayerP-,FutureNMOSTransistor,Photoresist,N-Well,Phosphorous（-）Ions,磷离子注入,磷离子注入高能磷离子注入形成局部N型区域，用于制造PMOS管,15,SiliconSubstrateP+,SiliconEpiLayerP-,FutureNMOSTransistor,N-Well,除去光刻胶,16,Photoresist,SiliconSubstrateP+,SiliconEpiLayerP-,FutureNMOSTransistor,N-Well,光刻胶成形,光刻胶成形厚度比较厚，用于阻挡离子注入用于P-阱的定义,17,SiliconSubstrateP+,SiliconEpiLayerP-,Photoresist,N-Well,Boron（+）Ions,P-Well,硼离子注入高能硼离子注入形成局部P型区域，用于制造NMOS管,硼离子注入,18,SiliconSubstrateP+,SiliconEpiLayerP-,N-Well,P-Well,除去光刻胶,19,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,退火,退火在6001000的H2环境中加热修复离子注入造成的Si表面晶体损伤注入杂质的电激活同时会造成杂质的进一步扩散快速加热工艺（RTP）可以减少杂质的扩散,20,TrenchOxide,N-Well,P-Well,CrossSection,完成N-阱和P-阱,平面视图,21,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,SacrificialOxide,牺牲氧化层生长,牺牲氧化层生长厚度约25nm用来捕获Si表面的缺陷,22,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,除去牺牲氧化层,除去牺牲氧化层HF溶液湿法刻蚀剩下洁净的Si表面,23,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,GateOxide,栅氧化层生长,栅氧化层生长工艺中最关键的一步厚度210nm要求非常洁净，厚度精确

（1）用作晶体管的栅绝缘层,24,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,Polysilicon,多晶硅淀积,多晶硅淀积厚度150300nm化学气相淀积（CVD）,25,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,Photoresist,ChannelLength,Polysilicon,光刻胶成形,光刻胶成形工艺中最关键的图形转移步骤栅长的精确性是晶体管开关速度的首要决定因素使用最先进的曝光技术深紫外光（DUV）光刻胶厚度比其他步骤薄,26,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,Photoresist,ChannelLength,多晶硅刻蚀,多晶硅刻蚀基于氟的反应离子刻蚀（RIE）必须精确的从光刻胶得到多晶硅的形状,27,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,GateOxide,PolyGateElectrode,除去光刻胶,28,TrenchOxide,N-Well,P-Well,CrossSection,Polysilicon,平面视图,完成栅极,29,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,GateOxide,PolyGateElectrode,PolyRe-oxidation,多晶硅氧化,多晶硅氧化在多晶硅表面生长薄氧化层用于缓冲隔离多晶硅和后续步骤形成的Si3N4,30,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,Photoresist,光刻胶成形,光刻胶成形用于控制NMOS管的衔接注入,31,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,Photoresist,Arsenic（-）Ions,NTip,NMOS管衔接注入,NMOS管衔接注入低能量、浅深度、低掺杂的砷离子注入衔接注入用于削弱栅区的热载流子效应,32,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,NTip,除去光刻胶,33,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,Photoresist,NTip,光刻胶成形,光刻胶成形用于控制PMOS管的衔接注入,34,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,Photoresist,BF2（+）Ions,NTip,PTip,PMOS管衔接注入低能量、浅深度、低掺杂的BF2+离子注入衔接注入用于削弱栅区的热载流子效应,PMOS管衔接注入,35,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,NTip,PTip,除去光刻胶,36,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,SiliconNitride,ThinnerHere,ThickerHere,NTip,PTip,PTip,Si3N4淀积,Si3N4淀积厚度120180nmCVD,37,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,SpacerSidewall,NTip,PTip,PTip,Si3N4刻蚀,Si3N4刻蚀水平表面的薄层Si3N4被刻蚀，留下隔离侧墙侧墙精确定位晶体管源区和漏区的离子注入RIE,38,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,Photoresist,NTip,PTip,光刻胶成形,光刻胶成形用于控制NMOS管的源/漏区注入,39,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,Photoresist,Arsenic（-）Ions,N+Drain,N+Source,PTip,NMOS管源/漏注入,NMOS管源/漏注入浅深度、重掺杂的砷离子注入，形成了重掺杂的源/漏区隔离侧墙阻挡了栅区附近的注入,40,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,PTip,除去光刻胶,41,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,Photoresist,PTip,光刻胶成形,光刻胶成形用于控制PMOS管的源/漏区注入,42,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,BF2（+）Ions,Photoresist,N+Drain,N+Source,P+Source,P+Drain,PMOS管源/漏注入,PMOS管源/漏注入浅深度、重掺杂的BF2+离子注入，形成了重掺杂的源/漏区隔离侧墙阻挡了栅区附近的注入,43,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Source,P+Drain,LightlyDoped“Tips”,除去光刻胶和退火,除去光刻胶和退火用RTP工艺，消除杂质在源/漏区的迁移,44,TrenchOxide,Polysilicon,CrossSection,N-Well,P-Well,N+Source/Drain,P+Source/Drain,Spacer,平面视图,完成晶体管源/漏极，电子器件形成,45,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,除去表面氧化物,除去表面氧化物在HF溶液中快速浸泡，使栅、源、漏区的Si暴露出来,46,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,Titanium,Ti淀积,Ti淀积厚度2040nm溅射工艺Ti淀积在整个晶圆表面,47,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,TitaniumSilicide,UnreactedTitanium,TiSi2形成,TiSi2形成RTP工艺，N2气氛，800在Ti和Si接触的区域，形成TiSi2其他区域的Ti没有变化称为自对准硅化物工艺（Salicide）,48,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,TitaniumSilicide,Ti刻蚀,Ti刻蚀NH4OH+H2O2湿法刻蚀未参加反应的Ti被刻蚀TiSi2保留下来，形成Si和金属之间的欧姆接触,49,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,BPSG淀积,硼磷硅玻璃（BPSG）淀积CVD，厚度约1umSiO2并掺杂少量硼和磷改善薄膜的流动性和禁锢污染物的性能这一层绝缘隔离器件和第一层金属,50,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,BPSG抛光,硼磷硅玻璃（BPSG）抛光CMP在BPSG层上获得一个光滑的表面,51,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,Photoresist,光刻胶成形,光刻胶成形用于定义接触孔（Contacts）这是一个关键的光刻步骤,52,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,Photoresist,接触孔刻蚀,接触孔刻蚀基于氟的RIE获得垂直的侧墙提供金属和底层器件的连接,53,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,除去光刻胶,54,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,TitaniumNitride,TiN淀积,TiN淀积厚度约20nm溅射工艺有助于后续的钨层附着在氧化层上,55,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,TitaniumNitride,Tungsten,钨淀积,钨淀积CVD厚度不少于接触孔直径的一半填充接触孔,56,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,钨抛光,钨抛光CMP除去表面的钨和TiN留下钨塞填充接触孔,57,TrenchOxide,Polysilicon,CrossSection,N-Well,P-Well,N+Source/Drain,P+Source/Drain,Spacer,Contact,平面视图,完成接触孔，多晶硅上的接触孔没有出现在剖面图上,58,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,Ti（200）-electromigrationshunt,TiN（500）-diffusionbarrier,Al-Cu（5000）-mainconductor,TiN（500）-antireflectivecoating,Metal1淀积,第一层金属淀积（Metal1）实际上由多个不同的层组成溅射工艺,59,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,Photoresist,光刻胶成形,光刻胶成形用于定义Metal1互连,60,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,Photoresist,Metal1刻蚀,Metal1刻蚀基于氯的RIE由于Metal1由多层金属组成，所以需要多个刻蚀步骤,61,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,除去光刻胶,62,TrenchOxide,Polysilicon,CrossSection,N-Well,P-Well,N+Source/Drain,P+Source/Drain,Spacer,Contact,Metal1,平面视图,完成第一层互连,63,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,IMD1,IMD淀积,金属间绝缘体（IMD）淀积未掺杂的SiO2连续的CVD和刻蚀工艺，厚度约1um填充在金属线之间，提供金属层之间的绝缘隔离,64,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,IMD1,IMD抛光,IMD抛光CMP,65,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,IMD1,Photoresist,光刻胶成形,光刻胶成形用于定义通孔（Vias）,66,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,Photoresist,IMD1,通孔刻蚀,通孔刻蚀基于氟的RIE，获得垂直的侧墙提供金属层之间的连接,67,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,IMD1,除去光刻胶,68,Tungsten,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,IMD1,WViaPlug,TiN和钨淀积,TiN和钨淀积同第一层互连,69,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,IMD1,WViaPlug,钨和TiN抛光,钨和TiN抛光同第一层互连,70,TrenchOxide,Polysilicon,CrossSection,N-Well,P-Well,N+Source/Drain,P+Source/Drain,Spacer,Contact,Metal1,Via1,平面视图,完成通孔,71,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,IMD1,WViaPlug,Metal2,Metal2淀积,Metal2淀积类似于Metal1厚度和宽度增加，连接更长的距离，承载更大的电流,72,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,Photoresist,IMD1,WViaPlug,Metal2,光刻胶成形,光刻胶成形相邻的金属层连线方向垂直，减小层间的感应耦合,73,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,Photoresist,IMD1,WViaPlug,Metal2,Metal2刻蚀,Metal2刻蚀类似于Metal1,74,SiliconSubstrateP+,SiliconEpiLayerP-,P-Well,N-Well,N+Drain,N+Source,P+Drain,P+Source,BPSG,WContactPlug,Metal1,IMD1,WViaP