清华大学模拟集成电路分析与设计第七讲 LPE与后仿真.pptx

清华大学模拟集成电路分析与设计第七讲 LPE与后仿真.pptx

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第七讲DraculaLVSLPE&Postsim分层设计李福乐OutlineLVS的常用设置与错误类型LPE/PRE版图寄生提取后仿真分层设计的几个问题LVSInternalFlowReaddatabaseTopcellnameExpanddataFromtopExtractdeviceandparametersFilterunuseddeviseReducedeviceasspecifiedBuiltmapofcorrespondenceTracefrompadsBuildDeviceAndnodemapsComparisonandOutputFilterunuseddevise*descriptionsystem=gds2filter-lay-opt=BCDEHJKORfilter-sch-opt=BCDEHJKOR在lvscommandfile中的设定语句B.gateisfloating,notconnecttoanypadthroughasource/drainC.gateconnecttopowerorgroundandeitherthesourceordrainisfloatD.gateisfloating,S/DnetshaveonlyaPOWERpathandnopathstoanypadEgateisfloating,S/DnetshaveonlyaGNDpathandnopathstoanypadFMOSNdevicesthathavethegatetiedtoaGROUNDGMOSPdevicesthathavethegatetiedtoaPOWERHwithboththesourceanddrainnetstiedtothePOWERFilterunuseddevise*descriptionsystem=gds2filter-lay-opt=BCDEHJKORfilter-sch-opt=BCDEHJKOR在lvscommandfile中的设定语句IwithboththesourceanddrainnetstiedtotheGROUNDJgatetiedtoeitherPOWERorGNDandsourceanddraintiedtogetherKwithsourceanddrainhavingnopathstoanypadLeithersourceordrainisfloatingRresistorsanddiodswithatleastonefloatingterminalUboththesourceanddrainarefloatingZfloatingbipolartransistors,diods,andresistorsLVSInitialNodePairsLVScomparisonusingtextextractedfromtheschematicandlayoutasastartingpointLVSresultheavilyrelyonthematchingofinputlabelsUseCPOINT-FILEcommand（in*Descriptionblock）tospecifythelabelmatchingoflayoutandschematic*DescriptionCPOINT-FILE=INITNAME.TXTInINITNAME.TXT:

LayoutnameingndSchematicnamevinvss现在用的lvs文件中没有这个command，要用的自己填加LVSCheckOption;lvschecks在lvscommandfile中的设定lvschkxrelpercent=0wpercent=0resval=1capval=1AsmashesseriescapacitaorsCfromsCMOSgatessuchasINVERTORs,NORs,NANDs,AOIs,andOAIsEusessizeinfomationtomatchMOS,BJTandresistorparalleldevicesFfilterstheunusedMOSdevices,forexample,gatearraysGfiltersboththeschematicandthelayoutinthesamewayKkeepsparalledevicesunsmashedLsameastheCoptionexpectdoesnotformAOIandOAIgatesOformsparallesandseriesMOSsturucturesevenifneitherisconnectedtopowerorgroundPcheckstheELEMENTcapacitorspolarityLVSCheckOption;lvscheckslvschkxrelpercent=0wpercent=0resval=1capval=1在lvscommandfile中的设定RsmashesseriesresistorsSsmashesMOSsplit-gatesthatareformedasSUPIorSDWIdevicestoasingleSUPorSDWdevice,respectivelyUreportsinthedescrepancyfile（.LVS）onlytheunmatchedschematicandunmatchedlayoutdevicesonmatchednodes（type4,5,and6LVSerrors）Xcarryesoutthecomparisonatthetaransistorlevel（thatis,noswapallowed）XdontusewithSorLoption.Zrandomlymatchesdeviceswithacommonmatchesterminalandotherterminalsfloating,andfiltersoutdeviceswithpathtoanytextpads所以在task1:

layout的电阻合并成1个了LVSDeviceReductionDraculaiscapableofperformingLVSuptogatelevelGateinformationisextractedfromlayoutbydevicereductionGateinformationisextractedstage-by-stagePrimitivestructuresbydeviceextractioninclude:

MOS,BJT,Res,DioandCapLVSDeviceReductionSecondLevelStructurePUPOut,IN1,IN2,SUPOut,IN1,IN2,LVSDeviceReductionSecondLevelStructurePDWOut,IN1,IN2,SDWOut,IN1,IN2,LVSDeviceReductionGateLevelStructurePUPIout1,IN1,IN2SUPOut,IN3,out1AOIOut,IN1,IN2,IN3SDWIout2,IN1,IN2PDWOut,IN3,out2LVSComparisonOptionProhibitInputSwappingLVSCHKxReduceSeriesResistorsLVSCHKrProhibitparallelReductionLVSCHKkLVSComparisonOptionReduceSeriesCapacitorsLVSCHKaSeriesMOSReductionLVSCHKsCMOSGateReductionLVSCHKcLVSCHKlL不能做到AOI和OAILVSParameterComparison;lvscheckslvschkxrelpercent=0wpercent=0resval=1capval=1SpecifythevaluetoleranceforparametercomparisonLpercent:

MOSlengthratioWpercent:

MOSwidthratioResval:

resistorvalueratioCapval:

capacitorvalueratioW/l-percent:

MOSaspectratioweffect=0.6:

CornereffecttoorthogonallybentgateLVSParameterComparison例：

将lvs中的resval改为20，重新对上一讲的例子task1做LVS检查，看修改前后的错误报告;lvscheckslvschkxrelpercent=0wpercent=0resval=20capval=1修改前的lvspr.lvsDEV2RESRP-RR0OUT,VDD!

SUB-TYPE=RPVALUE=15000.0:

DEV6RESP2:

X=-35.60Y=9.70OUT,VDD!

SUB-TYPE=P2VALUE=13570.5TOTAL1DISCREPANCYPOINTSREPORTED1*DISCREPANCYPOINTSLISTING*这部分给出了schematic与layout不一致的地方：

电阻模型名和阻值不一致！

*DISCREPANCY1*修改后的lvspr.lvsDEV2RESRP-RR0OUT,VDD!

SUB-TYPE=RP:

DEV6RESP2:

X=-35.60Y=9.70OUT,VDD!

SUB-TYPE=P2TOTAL1DISCREPANCYPOINTSREPORTED1*DISCREPANCYPOINTSLISTING*由于15k和13.57k之差小于resval规定的20%，所以认为阻值通过LVS*DISCREPANCY1*.lvsLVSDebugLVS报告在lvspr.lvs中其结构和内容上一讲已经通过例子来介绍过LVSerror比DRCerror要难以debug若设计中有子单元，一般先检查底层子单元，待其全部正确后再检查顶层单元LVS结果与指定的pin,label等密切相关，所以在指定时一定不要弄错很多error都是相关的，一个error可能会连锁导致很多error，故修正一个后马上重做LVS要debugLVSerror，须熟知errortypes，所有的errortype可在矛盾点列表（Discrepancypointlisting）中查看LVSErrorTypesType2:

MATCHEDDEVICETOUNMATCHEDNODE总共15种errortypesType1:

MATCHEDNODETONODEVICELVSErrorTypesType3:

INCONSISTENTLYMATCHEDDEVICEType4:

MatchedNodetoExtraLayoutDevicesLVSErrorTypesType5:

MatchedNodetoExtraSchematicDevicesType6:

MatchedNodetoUnmatchedLayoutandSchematicDevicesLVSErrorTypesType7:

OtherUnmatchedLayoutDevicesThistypeoferrorindicatethoselayoutdeviceswhichareeitherseparatedfromrestofcircuitorcannotbereachedfrominitialcorrenspondencepointsorblockedbydiscrepancypointsType8:

OtherUnmatchedSchematicDevicesThistypeoferrorindicatethoseschematicdeviceswhichareeitherseparatedfromrestofcircuitorcannotbereachedfrominitialcorrenspondencepointsorblockedbydiscrepancypointsLVSErrorTypesType9:

DeviceSubtypeMismatchType10:

DeviceSizeMismatchLVSErrorTypesType11:

MOSReversibilityErrorType12:

DeviceSubstrateConnectionMismatchType13:

DevicePowerConnectionMismatchLVSErrorTypesType14:

ReducedLayoutParallelDevicesThistypeisforreferenceonlyType15:

Filtered-outLayoutMOSDevicesThistypeisforreferenceonlyLPE（LayoutParameterExtraction）LayoutstreamoutGDSIILPENetlistPostlayoutSimulationHspiceSchematicNetlistDRCLVSLPE在LVS正确后，提取版图器件参数和寄生参数LPELOGLVSLVSLOGIC.DATLPENET.DATLayoutStreamOutGDSIIDatabaseSchematicCDLOutCDLNetlist修改LPECommandfilecd./verifyPDRACULA:

/glpe:

/取得LPECommandfileCdlout的网表，Streamout的gdsiifile，Commandfile等最好都放在一个专用目录下，如/project/verifyLPENetlist做LPE时，schematic和layout中的元件类型、数量、相互间的连接关系必须一致，即电路拓扑必须一致，否则会产生错误若schematic和layout中元件的参数不一样，则以layout中提取出来的值为准提取的参数主要包括元件参数（如mos管W/L，AD，PD，AS，PS，电阻阻值，电容容值等）和节点的寄生电容提出出来的Netlist符合Hspcie格式LPE的例子仍以第三讲中的第一个版图设计作业为例lab:

task1:

schematiclab:

task1:

layout寄生提取与网表反标注查看LPENET.DAT*MM0OUTINGND!

GND!

NL=0.80UW=6.00UAD=9.60PPD=15.20UAS=5.40P+PS=7.80UMM0-1OUTINGND!

GND!

NL=0.80UW=6.00UAD=5.55PPD=7.85UAS=5.40P+PS=7.80UMM0-2OUTINGND!

GND!

NL=0.80UW=6.00UAD=5.55PPD=7.85UAS=5.40P+PS=7.80UMM0-3OUTINGND!

GND!

NL=0.80UW=6.00UAD=5.40PPD=7.80UAS=5.40P+PS=7.80UMM0-4OUTINGND!

GND!

NL=0.80UW=6.00UAD=5.40PPD=7.80UAS=9.60P+PS=15.20U*-TOTAL#OFMOSTRANSISTORSFOUND:

5原来netlist里没定义的，根据版图新提出来的参数*-COMMENTED:

0须为0！

否则表示layout和schematic中的MOS管没有完全对应好寄生提取-晶体管MM0-4MM0h1wh2MM0-1对于MM0的D端：

ADw*h1PD2w+2h1对于MM0-1的D端：

ADw*h2PDwh其他类推查看LPENET.DAT*RESISTORSPARAMETERSFROM:

7RESXREF*RR0OUTVDD!

R1.35705E04*-TOTAL#OFRESISTORSFOUND:

*-COMMENTED:

01须为0！

查看LPENET.DAT*CAPACITORSPARAMETERSFROM:

7CAPXREFCAPACITORSPARAMETERSFROM:

7CAPXMER*C1OUTGND!

1.10627E-15C2INGND!

3.07552E-15C3OUTGND!

1.03680E-16C4OUTGND!

2.07360E-16*-TOTAL#OFCAPSFOUND:

*-COMMENTED:

0*4.ENDS原来Schematic中没有的，根据layout提出出来的电路节点寄生电容PRE（ParasiticResistanceExtraction）从上面的LPENET.DAT可知，lpe中只给出了提取元件参数和节点寄生电容的操作为了更精确地模拟电路工作，除了提取元件参数和节点寄生电容外，还需提取寄生电阻，即PRE上华提供了PREcommandfile，实际上是在lpe的基础上，增加了提取寄生电阻的操作仍以第三讲中的第一个版图作业为例PRELOGLVSLVSLOGIC.DATPRENET.DATLayoutStreamOutGDSIIDatabaseSchematicCDLOutCDLNetlist修改PRECommandfilecd./verifyPDRACULA:

/gpre:

/取得PRECommandfileCdlout的网表，Streamout的gdsiifile，Commandfile等最好都放在一个专用目录下，如/project/verify查看PRENET.DAT*MM0OUT:

5IN:

9GND!

GND!

NL=0.80UW=6.00UAD=9.60PPD=15.20UAS=5.40P+PS=7.80UMM0-1OUT:

7IN:

10GND!

GND!

NL=0.80UW=6.00UAD=5.55PPD=7.85U+AS=5.40PPS=7.80UMM0-2OUT:

7IN:

11GND!

GND!

NL=0.80UW=6.00UAD=5.55PPD=7.85U+AS=5.40PPS=7.80UMM0-3OUT:

9IN:

12GND!

GND!

NL=0.80UW=6.00UAD=5.40PPD=7.80U+AS=5.40PPS=7.80UMM0-4OUT:

9IN:

13GND!

GND!

NL=0.80UW=6.00UAD=5.40PPD=7.80U+AS=9.60PPS=15.20U*-TOTAL#OFMOSTRANSISTORSFOUND:

5*-COMMENTED:

0须为0！

否则表示layout和schematic中的MOS管没有完全对应好注意MOS管D、G端的节点名查看PRENET.DAT*RESISTORSPARAMETERSFROM:

7RESXREF*RR0OUT:

12OUT:

4R3.39263E03RR0-1OUT:

13OUT:

14R3.39263E03RR0-2OUT:

16OUT:

15R3.39263E03RR0-3OUT:

17VDD!

R3.39263E03*-TOTAL#OFRESISTORSFOUND:

4*-COMMENTED:

0注意要考虑电阻端口间的寄生，故没有象LPE那样reduce为一个电阻查看PRENET.DAT*R10OUTOUT:

24.53497E-02R11OUTOUT:

36.98120E-02R12OUT:

2OUT:

47.01360E-02R13OUT:

3OUT:

61.09479E-01R14ININ:

26.41667E-02R15OUT:

5OUT:

65.08458E-02R16OUT:

12OUT:

131.88889E-01*R17GND!

GND!

:

31.02778E-01R18OUT:

6OUT:

82.21308E-01R19IN:

2IN:

33.54167E-02*R20GND!

:

2GND!

:

32.11111E-01*R21GND!

:

3GND!

:

56.56950E-02RESISTORSPARAMETERSFROM:

7RESPREF提取出了寄生电阻！

寄生电阻部分

（1）对照版图，结合前面MOS管的节点，仔细分析这些电阻的分布，找出提取的规律参考precommandfile查看PRENET.DATR22OUT:

14OUT:

151.88889E-01R23OUT:

7OUT:

85.08458E-02R24IN:

3IN:

43.54167E-02R25OUT:

8OUT:

102.22724E-01*R26GND!

:

4GND!

:

52.38114E-01R27IN:

4IN:

53.33333E-02*R28GND!

:

5GND!

:

78.89198E-02R29OUT:

16OUT:

171.88889E-01R30IN:

5IN:

63.33333E-02R31OUT:

9OUT:

105.59105E-02R32IN:

6IN:

71.66925E-01*R33GND!

:

6GND!

:

72.30169E-01*R34VDD!

VDD!

:

31.40120E-01寄生电阻部分

（2）查看PRENET.DATR35IN:

7IN:

82.29544E-01*R36VDD!

:

2VDD!

:

31.39566E-01R37IN:

2IN:

92.62500E01R38IN:

3IN:

102.62500E01R39IN:

4IN:

112.62500E01R40IN:

5IN:

122.62500E01R41IN:

6IN:

132.62500E01R42OUTOUT:

117.70667E-02R43IN:

8IN:

141.58400E-01*-TOTAL#OFRESISTORSFOUND:

*-COMMENTED:

834寄生电阻部分（3）寄生部分不为0并不表示layout与schematic没有对应好查看PRENET.DATC1OUTGND!

1.75988E-16C2INGND!

8.06400E-17C3C4C5C6C7C8C9C10C1