EDA花样流水灯.docx
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EDA花样流水灯
EDA大作业
流水灯设计
基于QuartusII的花样流水灯的设计
流水灯是一串按一定的规律像流水一样连续闪亮，流水灯控制是可编程控制器的一个应用，其控制思想在工业控制技术领域也同样适用。
流水灯控制可用多种方法实现，但对现代可编程控制器而言，基于EDA技术的流水灯设计也是很普遍的。
1.设计目的
a.学习使用EDA集成设计软件QuartusII，电路描述，综合，模拟过程
b.了解基于EDA应用系统的设计方法
c.掌握使用EDA工具设计流水灯的设计思路和设计方法
d.熟练使用QuartusII对实验程序进行改错，调试以及演示现象
2.设计说明
流水灯设计是由八只LED显示灯来实现的，通过程序代码来控制这八只灯的亮灭，从而实现花型的变化（快慢，顺序）。
3．程序设计
3.1
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYfirstIS
PORT（
clk:
INstd_logic;
rst:
INstd_logic;
c:
OUTstd_logic_vector（7DOWNTO0）
）;
ENDfirst;
ARCHITECTUREarchOFfirstIS
CONSTANTstate0:
std_logic_vector（2DOWNTO0）:
="000";
CONSTANTstate1:
std_logic_vector（2DOWNTO0）:
="001";
CONSTANTstate2:
std_logic_vector（2DOWNTO0）:
="010";
CONSTANTstate3:
std_logic_vector（2DOWNTO0）:
="011";
CONSTANTstate4:
std_logic_vector（2DOWNTO0）:
="100";
CONSTANTstate5:
std_logic_vector（2DOWNTO0）:
="101";
CONSTANTstate6:
std_logic_vector（2DOWNTO0）:
="110";
CONSTANTstate7:
std_logic_vector（2DOWNTO0）:
="111";
SIGNALstate:
std_logic_vector（2DOWNTO0）;
SIGNALcnt:
std_logic_vector（2DOWNTO0）;
BEGIN
PROCESS（clk,rst）
BEGIN
IF（NOTrst='1'）THEN
state<=state0;
cnt<="000";
ELSIF（clk'EVENTANDclk='1'）THEN
cnt<=cnt+"001";
IF（cnt="111"）THEN
CASEstateIS
WHENstate0=>
state<=state1;
WHENstate1=>
state<=state2;
WHENstate2=>
state<=state3;
WHENstate3=>
state<=state4;
WHENstate4=>
state<=state5;
WHENstate5=>
state<=state6;
WHENstate6=>
state<=state7;
WHENstate7=>
state<=state0;
WHENOTHERS=>NULL;
ENDCASE;
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS（state）
BEGIN
CASEstateIS
WHENstate0=>
c<="10101010";
WHENstate1=>
c<="01010101";
WHENstate2=>
c<="10101010";
WHENstate3=>
c<="01010101";
WHENstate4=>
c<="10101010";
WHENstate5=>
c<="01010101";
WHENstate6=>
c<="10101010";
WHENstate7=>
c<="01010101";
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
ENDarch;
3.2
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYsecondIS
PORT（
clk:
INstd_logic;
rst:
INstd_logic;
c:
OUTstd_logic_vector（7DOWNTO0）
）;
ENDsecond;
ARCHITECTUREarchOFsecondIS
CONSTANTstate0:
std_logic_vector（2DOWNTO0）:
="000";
CONSTANTstate1:
std_logic_vector（2DOWNTO0）:
="001";
CONSTANTstate2:
std_logic_vector（2DOWNTO0）:
="010";
CONSTANTstate3:
std_logic_vector（2DOWNTO0）:
="011";
CONSTANTstate4:
std_logic_vector（2DOWNTO0）:
="100";
CONSTANTstate5:
std_logic_vector（2DOWNTO0）:
="101";
CONSTANTstate6:
std_logic_vector（2DOWNTO0）:
="110";
CONSTANTstate7:
std_logic_vector（2DOWNTO0）:
="111";
SIGNALstate:
std_logic_vector（2DOWNTO0）;
SIGNALcnt:
std_logic_vector（2DOWNTO0）;
BEGIN
PROCESS（clk,rst）
BEGIN
IF（NOTrst='1'）THEN
state<=state0;
cnt<="000";
ELSIF（clk'EVENTANDclk='1'）THEN
cnt<=cnt+"001";
IF（cnt="111"）THEN
CASEstateIS
WHENstate0=>
state<=state1;
WHENstate1=>
state<=state2;
WHENstate2=>
state<=state3;
WHENstate3=>
state<=state4;
WHENstate4=>
state<=state5;
WHENstate5=>
state<=state6;
WHENstate6=>
state<=state7;
WHENstate7=>
state<=state0;
WHENOTHERS=>NULL;
ENDCASE;
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS（state）
BEGIN
CASEstateIS
WHENstate0=>
c<="10000000";
WHENstate1=>
c<="01000000";
WHENstate2=>
c<="00100000";
WHENstate3=>
c<="00010000";
WHENstate4=>
c<="00001000";
WHENstate5=>
c<="00000100";
WHENstate6=>
c<="00000010";
WHENstate7=>
c<="00000001";
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
ENDarch;
3.3
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYthirdIS
PORT（
clk:
INstd_logic;
rst:
INstd_logic;
c:
OUTstd_logic_vector（7DOWNTO0）
）;
ENDthird;
ARCHITECTUREarchOFthirdIS
CONSTANTstate0:
std_logic_vector（2DOWNTO0）:
="000";
CONSTANTstate1:
std_logic_vector（2DOWNTO0）:
="001";
CONSTANTstate2:
std_logic_vector（2DOWNTO0）:
="010";
CONSTANTstate3:
std_logic_vector（2DOWNTO0）:
="011";
CONSTANTstate4:
std_logic_vector（2DOWNTO0）:
="100";
CONSTANTstate5:
std_logic_vector（2DOWNTO0）:
="101";
CONSTANTstate6:
std_logic_vector（2DOWNTO0）:
="110";
CONSTANTstate7:
std_logic_vector（2DOWNTO0）:
="111";
SIGNALstate:
std_logic_vector（2DOWNTO0）;
SIGNALcnt:
std_logic_vector（2DOWNTO0）;
BEGIN
PROCESS（clk,rst）
BEGIN
IF（NOTrst='1'）THEN
state<=state0;
cnt<="000";
ELSIF（clk'EVENTANDclk='1'）THEN
cnt<=cnt+"001";
IF（cnt="111"）THEN
CASEstateIS
WHENstate0=>
state<=state1;
WHENstate1=>
state<=state2;
WHENstate2=>
state<=state3;
WHENstate3=>
state<=state4;
WHENstate4=>
state<=state5;
WHENstate5=>
state<=state6;
WHENstate6=>
state<=state7;
WHENstate7=>
state<=state0;
WHENOTHERS=>NULL
ENDCASE;
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS（state）
BEGIN
CASEstateIS
WHENstate0=>
c<="00000001";
WHENstate1=>
c<="00000010";
WHENstate2=>
c<="00000100";
WHENstate3=>
c<="00001000";
WHENstate4=>
c<="00010000";
WHENstate5=>
c<="00100000";
WHENstate6=>
c<="01000000";
WHENstate7=>
c<="10000000";
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
ENDarch;
3.4
libraryieee;
useieee.std_logic_1164.all;
entitysanbais
port（a,b,c:
instd_logic;
y7,y6,y5,y4,y3,y2,y1,y0:
outstd_logic）;
endentitysanba;
architecturebehavofsanbais
signalabc:
std_logic_vector（2downto0）;
begin
abc<=a&b&c;
process（a,b,c）
begin
caseabcis
when"000"=>y0<='0';y1<='1';y2<='1';y3<='1';y4<='1';y5<='1';y6<='1';y7<='1';
when"001"=>y0<='1';y1<='0';y2<='1';y3<='1';y4<='1';y5<='1';y6<='1';y7<='1';
when"010"=>y0<='1';y1<='1';y2<='0';y3<='1';y4<='1';y5<='1';y6<='1';y7<='1';
when"011"=>y0<='1';y1<='1';y2<='1';y3<='0';y4<='1';y5<='1';y6<='1';y7<='1';
when"100"=>y0<='1';y1<='1';y2<='1';y3<='1';y4<='0';y5<='1';y6<='1';y7<='1';
when"101"=>y0<='1';y1<='1';y2<='1';y3<='1';y4<='1';y5<='0';y6<='1';y7<='1';
when"110"=>y0<='1';y1<='1';y2<='1';y3<='1';y4<='1';y5<='1';y6<='0';y7<='1';
when"111"=>y0<='1';y1<='1';y2<='1';y3<='1';y4<='1';y5<='1';y6<='1';y7<='0';
whenothers=>
endcase;
endprocess;
endarchitecturebehav;
3.5libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYfirstIS
PORT（
clk:
INstd_logic;
rst:
INstd_logic;
c:
OUTstd_logic_vector（7DOWNTO0）
）;
ENDfirst;
ARCHITECTUREarchOFfirstIS
CONSTANTstate0:
std_logic_vector（2DOWNTO0）:
="000";
CONSTANTstate1:
std_logic_vector（2DOWNTO0）:
="001";
CONSTANTstate2:
std_logic_vector（2DOWNTO0）:
="010";
CONSTANTstate3:
std_logic_vector（2DOWNTO0）:
="011";
CONSTANTstate4:
std_logic_vector（2DOWNTO0）:
="100";
CONSTANTstate5:
std_logic_vector（2DOWNTO0）:
="101";
CONSTANTstate6:
std_logic_vector（2DOWNTO0）:
="110";
CONSTANTstate7:
std_logic_vector（2DOWNTO0）:
="111";
SIGNALstate:
std_logic_vector（2DOWNTO0）;
SIGNALcnt:
std_logic_vector（2DOWNTO0）;
BEGIN
PROCESS（clk,rst）
BEGIN
IF（NOTrst='1'）THEN
state<=state0;
cnt<="000";
ELSIF（clk'EVENTANDclk='1'）THEN
cnt<=cnt+"001";
IF（cnt="111"）THEN
CASEstateIS
WHENstate0=>
state<=state1;
WHENstate1=>
state<=state2;
WHENstate2=>
state<=state3;
WHENstate3=>
state<=state4;
WHENstate4=>
state<=state5;
WHENstate5=>
state<=state6;
WHENstate6=>
state<=state7;
WHENstate7=>
state<=state0;
WHENOTHERS=>NULL;
ENDCASE;
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS（state）
BEGIN
CASEstateIS
WHENstate0=>
c<="10101010";
WHENstate1=>
c<="11000000";
WHENstate2=>
c<="01100000";
WHENstate3=>
c<="00110000";
WHENstate4=>
c<="00011000";
WHENstate5=>
c<="00001100";
WHENstate6=>
c<="00000110";
WHENstate7=>
c<="00000011";
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
ENDarch;
3.6libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYfirstIS
PORT（
clk:
INstd_logic;
rst:
INstd_logic;
c:
OUTstd_logic_vector（7DOWNTO0）
）;
ENDfirst;
ARCHITECTUREarchOFfirstIS
CONSTANTstate0:
std_logic_vector（2DOWNTO0）:
="000";
CONSTANTstate1:
std_logic_vector（2DOWNTO0）:
="001";
CONSTANTstate2:
std_logic_vector（2DOWNTO0）:
="010";
CONSTANTstate3:
std_logic_vector（2DOWNTO0）:
="011";
CONSTANTstate4:
std_logic_vector（2DOWNTO0）:
="100";
CONSTANTstate5:
std_logic_vector（2DOWNTO0）:
="101";
CONSTANTstate6:
std_logic_vector（2DOWNTO0）:
="110";
CONSTANTstate7:
std_logic_vector（2DOWNTO0）:
="111";
SIGNALstate:
std_logic_vector（2DOWNTO0）;
SIGNALcnt:
std_logic_vector（2DOWNTO0）;
BEGIN
PROCESS（clk,rst）
BEGIN
IF（NOTrst='1'）THEN
state<=state0;
cnt<="000";
ELSIF（clk'EVENTANDclk='1'）THEN
cnt<=cnt+"001";
IF（cnt="111"）THEN
CASEstateIS
WHENstate0=>
state<=state1;
WHENstate1=>
state<=state2;
WHENstate2=>
state<=state3;
WHENstate3=>
state<=state4;
WHENstate4=>
state<=state5;
WHENstate5=>
state<=state6;
WHENstate6=>
state<=state7;
WHENstate7=>
state<=state0;
WHENOTHERS=>NULL;
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