AEC Q100.docx
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AECQ100
Automotive Electronics Council
Page 1 of
3
Appendix 2:
Q100 Certification of Design, Construction and Qualification
Supplier Name:
Date:
The following information is required to identify a device that has met the requirements of AEC-Q100. Submission of the
required data in the format shown below is optional.
All
entries
must
be
completed;
if
a
particular
item
does
not
apply, enter "Not Applicable".
This template can be downloaded from the AEC website at .
This template is available as a stand-alone document.
Item Name
Supplier Response
1.
User’s Part Number:
2.
Supplier’s Part Number/Data Sheet:
3.
Device Description:
4.
Wafer/Die Fab Location & Process ID:
a.
Facility name/plant #:
b.
Street address:
c.
Country:
5.
Wafer Probe Location:
a.
Facility name/plant #:
b.
Street address:
c.
Country:
6.
Assembly Location & Process ID:
a.
Facility name/plant #:
b.
Street address:
c.
Country:
7.
Final Quality Control A （Test） Location:
a.
Facility name/plant #:
b.
Street address:
c.
Country:
8.
Wafer/Die:
a.
Wafer size:
b.
Die family:
c.
Die mask set revision & name:
d.
Die photo:
See attached
Not available
9.
Wafer/Die Technology Description:
a.
Wafer/Die process technology:
b.
Die channel length:
c.
Die gate length:
d.
Die supplier process ID （Mask #）:
e.
Number of transistors or gates:
f.
Number of mask steps:
10.
Die Dimensions:
a.
Die width:
b.
Die length:
c.
Die thickness （finished）:
11.
Die Metallization:
a.
Die metallization material（s）:
b.
Number of layers:
c.
Thickness （per layer）:
d.
% of alloys （if present）:
12.
Die Passivation:
a.
Number of passivation layers:
b.
Die passivation material（s）:
c.
Thickness（es） & tolerances:
13.
Die Overcoat Material （e.g., Polyimide）:
AEC - Q100 - Rev G
May 14, 2007
Component Technical Committee
Automotive Electronics Council
Page 2 of
3
14.
Die Cross-Section Photo/Drawing:
See attached
Not available
15.
Die Prep Backside:
a.
Die prep method:
b.
Die metallization:
c.
Thickness（es） & tolerances:
16.
Die Separation Method:
a.
Kerf width （
μ
m）:
b.
Kerf depth （if not 100% saw）:
c.
Saw method:
Single
Dual
17.
Die Attach:
a.
Die attach material ID:
b.
Die attach method:
c.
Die placement diagram:
See attached
Not available
18.
Package:
a.
Type of package （e.g., plastic, ceramic,
unpackaged）:
b.
Ball/lead count:
c.
JEDEC designation （e.g., MS029,
MS034, etc.）:
d.
Lead （Pb） free （< 0.1% homogenous
material）:
e.
Package outline drawing:
Yes
No
See attached
Not available
19.
Mold Compound:
a.
Mold compound supplier & ID:
b.
Mold compound type:
c.
Flammability rating:
d.
Fire Retardant type/composition:
e.
Tg （glass transition temperature）（
︒
C）:
f.
CTE （above & below Tg）（ppm/
︒
C）:
UL 94 V1
UL 94 V0
CTE1 （above Tg） =
CTE2 （below Tg） =
20.
Wire Bond:
a.
Wire bond material:
b.
Wire bond diameter （mils）:
c.
Type of wire bond at die:
d.
Type of wire bond at leadframe:
e.
Wire bonding diagram:
See attached
Not available
21.
Leadframe （if applicable）:
a.
Paddle/flag material:
b.
Paddle/flag width （mils）:
c.
Paddle/flag length （mils）:
d.
Paddle/flag plating composition:
e.
Paddle/flag plating thickness （
μ
inch）:
f.
Leadframe material:
g.
Leadframe bonding plating composition:
h.
Leadframe bonding plating thickness
（
μ
inch）:
i.
External lead plating composition:
j.
External lead plating thickness （
μ
inch）:
22.
Substrate （if applicable）:
a.
Substrate material （e.g., FR5, BT, etc.）:
b.
Substrate thickness （mm）:
c.
Number of substrate metal layers:
d.
Plating composition of ball solderable
surface:
e.
Panel singulation method:
f.
Solder ball composition:
g.
Solder ball diameter （mils）:
AEC - Q100 - Rev G
May 14, 2007
Component Technical Committee
Automotive Electronics Council
Page 3 of
3
23.
Unpackaged Die （if not packaged）:
a.
Under Bump Metallurgy （UBM）
composition:
b.
Thickness of UBM metal:
c.
Bump composition:
d.
Bump size:
24.
Header Material （if applicable）:
25.
Thermal Resistance:
a.
θ
JA
︒
C/W （approx）:
b.
θ
JC
︒
C/W （approx）:
c.
Special thermal dissipation construction
techniques:
26.
Test circuits, bias levels, & operational
conditions imposed during the supplier’s life
and environmental tests:
See attached
Not available
27.
Fault Grade Coverage （%）
%
Not digital circuitry
28.
Maximum Process Exposure Conditions:
a.
MSL @ rated SnPb temperature:
b.
MSL @ rated Pb-free temperature:
c.
Maximum dwell time @ maximum
process temperature:
* Note:
Temperatures are as measured on the center of
the plastic package body top surface.
at
︒
C （SnPb）
at
︒
C （Pb-free）
Attachments:
Requirements:
Die Photo
1. A separate Certification of Design, Construction &
Qualification must be submitted for each P/N, wafer fab,
and assembly location.
Package Outline Drawing
Die Cross-Section Photo/Drawing
Wire Bonding Diagram
2. Certification of Design, Construction & Qualification
shall be signed by the responsible individual at the
supplier who can verify the above information is
accurate and complete. Type/Print name and sign
below.
Die Placement Diagram
Test Circuits, Bias Levels, &
Conditions
Completed by:
Date:
Certified by:
Date:
Typed or
Printed:
Signature:
升级会员 