EDA试验数字时钟实验报告Word格式.docx
《EDA试验数字时钟实验报告Word格式.docx》由会员分享,可在线阅读,更多相关《EDA试验数字时钟实验报告Word格式.docx(13页珍藏版)》请在冰点文库上搜索。
OUTSTD_LOGIC;
hourhset:
OUTINTEGERRANGE0TO2;
hourlset:
OUTINTEGERRANGE0TO9;
minhset:
OUTINTEGERRANGE0TO5;
minlset:
sechset:
seclset:
OUTINTEGERRANGE0TO9);
ENDcontrol;
ARCHITECTUREarchiOFcontrolIS
TYPESTATEIS(sethh,sethl,setmh,setml,setsh,setsl,ini);
SIGNALadjsta:
STATE;
SIGNALsetmark:
STD_LOGIC;
SIGNALseclow,minlow,hourlow:
INTEGERRANGE0TO9;
SIGNALsechigh,minhigh:
INTEGERRANGE0TO5;
SIGNALhourhigh:
INTEGERRANGE0TO2;
BEGIN
seclset<
=seclow;
sechset<
=sechigh;
minlset<
=minlow;
minhset<
=minhigh;
hourlset<
=hourlow;
hourhset<
=hourhigh;
settime<
=setmark;
mark:
PROCESS(begend)
begin
ifreset='
1'
then
setmark<
='
0'
;
elsifbegend'
eventandbegend='
then
ifsetmark='
else
endif;
ENDPROCESS;
normal_run:
PROCESS(enter,reset)
IFreset='
THEN
adjsta<
=ini;
ELSIFenter='
ANDenter'
eventTHEN
caseadjstaIS
WHENini=>
=sethh;
WHENsethh=>
=sethl;
WHENsethl=>
=setmh;
WHENsetmh=>
=setml;
WHENsetml=>
=setsh;
WHENsetsh=>
=setsl;
WHENsetsl=>
endcase;
ENDIF;
time_adjust:
PROCESS(keyup)
hourhigh<
=0;
hourlow<
minhigh<
minlow<
sechigh<
seclow<
elsifkeyup='
ANDkeyup'
=hourhigh+1;
=hourlow+1;
=minhigh+1;
=minlow+1;
=sechigh+1;
=seclow+1;
NULL;
ENDarchi;
走时电路:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entityclockis
port(clk:
instd_logic;
inintegerrange0to2;
inintegerrange0to9;
inintegerrange0to5;
hourhdis:
outintegerrange0to2;
hourldis:
outintegerrange0to9;
minhdis:
outintegerrange0to5;
minldis:
sechdis:
secldis:
outintegerrange0to9);
endclock;
architecturearchiofclockis
signalseclow,minlow,hourlow:
integerrange0to9;
signalsechigh,minhigh:
integerrange0to5;
signalhourhigh:
integerrange0to2;
begin
secldis<
sechdis<
minldis<
minhdis<
hourldis<
hourhdis<
normal_run:
process(clk,settime)
begin
ifsettime='
seclow<
=seclset;
sechigh<
=sechset;
minlow<
=minlset;
minhigh<
=minhset;
hourlow<
=hourlset;
hourhigh<
=hourhset;
else
ifclk='
andclk'
eventthen
ifseclow=9thenseclow<
ifsechigh=5thensechigh<
ifminlow=9thenminlow<
ifminhigh=5thenminhigh<
ifhourlow=9then
hourlow<
hourhigh<
elsifhourlow=3andhourhigh=2then
elsehourlow<
endif;
elseminhigh<
endif;
elseminlow<
endif;
elsesechigh<
endif;
elseseclow<
endif;
endif;
endif;
endprocess;
endarchi;
打铃控制电路:
entityringis
port(reset:
alarm:
outstd_logic;
inintegerrange0to9);
endring;
architecturearchiofringis
constantre:
integer:
=2;
constantstop:
=50;
signalcnt:
integerrange0to60;
process(secldis)
begin
cnt<
=sechdis*10+secldis;
ifreset='
thenalarm<
elsif(minhdis=5andminldis=9)then
ifcnt>
stopandcnt<
re+stopthenalarm<
elsifcnt>
re+stopandcnt<
re*2+stopthenalarm<
2*re+stopandcnt<
4*re+stopthenalarm<
elsealarm<
elsealarm<
显示电路:
(2)设计模块及接口:
(3)选择可编程逻辑器件:
实验室里提供的是EP1K30QC208-3。
(4)指定管脚:
(5)编译文件,如图所示,编译成功:
(6)设定接口类型,选择ByteBlaster
(6)通过JTAG接口将程序下载到芯片
(7)观察实验板上的情况,调节相应开关,实验结果与预想一致。
三.实验总结
此次试验是我第一次做EDA试验,由于第一次学习使用,自然遇到了一些意想不到的问题,通过老师的悉心指导,与同学的互相交流,自己的实践总结经验把问题都最终解决。
设计平台Max+Plus2相对简洁易用,我感受到了可编程芯片的强大能力。
这次的数字电子钟采用的是从上至下的设计方法,实验结果也与预想一致。