数字钟编码Word格式.docx

数字钟编码Word格式.docx

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mh_set,sh_set:

instd_logic_vector（2downto0）;

--分,秒高位调整;

hl_set,ml_set,sl_set:

instd_logic_vector（3downto0）;

--时,分,秒低位调整;

led_dp:

outstd_logic;

--LED小数点;

sel:

outstd_logic_vector（2downto0）;

--送三-八译码生成位选信号;

seg:

outstd_logic_vector（6downto0））;

--段码;

endmyclock;

architectureoneofmyclockis

componentbclockis

port（clk,reset:

hhin:

mhin,shin:

hlin,mlin,slin:

hho:

outstd_logic_vector（1downto0）;

mho,sho:

hlo,mlo,slo:

outstd_logic_vector（3downto0））;

endcomponentbclock;

componentledctrlis 

port（clk:

hh:

mh,sh:

hl,ml,sl:

dp:

selo:

sego:

endcomponentledctrl;

signalhh1:

std_logic_vector（1downto0）;

signalmh1,sh1:

std_logic_vector（2downto0）;

signalhl1,ml1,sl1:

std_logic_vector（3downto0）;

begin

u1:

bclockportmap（clk1,reset,hh_set,mh_set,sh_set,hl_set,ml_set,sl_set,hh1,mh1,sh1,hl1,ml1,sl1）;

u2:

ledctrlportmap（clk2,hh1,mh1,sh1,hl1,ml1,sl1,led_dp,sel,seg）;

endone;

十进制数器

counter10.vhd

useieee.std_logic_unsigned.all;

entitycounter10is

din:

c:

dout:

endcounter10;

architectureoneofcounter10is

signaldd:

signalc1:

std_logic;

process（clk,reset）is

ifreset='

1'

thendd<

=din;

c1<

='

0'

;

elsifrising_edge（clk）then 

ifdd="

1001"

="

0000"

elsedd<

=dd+1;

endif;

endprocess;

dout<

=dd;

c<

=c1;

--*****************************************************

六进制计数器

counter6.vhd

--******************************************************

entitycounter6is

outstd_logic_vector（2downto0））;

endcounter6;

architectureoneofcounter6is

101"

000"

二十四进制数器

counter24.vhd

entitycounter24is

dhin:

dlin:

dh:

outstd_logic_vector（1downto0）;

dl:

endcounter24;

architectureoneofcounter24is

signaldl1:

signaldh1:

begin 

ifreset='

thendl1<

=dlin;

dh1<

=dhin;

elsifrising_edge（clk）then 

ifdh1="

10"

anddl1="

0011"

dh1<

00"

elsifdl1="

=dh1+1;

elsedl1<

=dl1+1;

endif;

dh<

=dh1;

dl<

=dl1;

--*******************************************************

时钟模块

bclock.vhd

entitybclockis

endbclock;

architectureoneofbclockis

componentcounter10is

end 

componentcounter10;

componentcounter6is

componentcounter6;

component 

counter24is

endcomponentcounter24;

signalcsl,csh,cml,cmh:

u1:

counter10portmap（clk,reset,slin,csl,slo）;

u2:

counter6portmap（csl,reset,shin,csh,sho）;

u3:

counter10portmap（csh,reset,mlin,cml,mlo）;

u4:

counter6portmap（cml,reset,mhin,cmh,mho）;

u5:

counter24portmap（cmh,reset,hhin,hlin,hho,hlo）;

LED扫描显示模块

ledctrl.vhd

--*********************************************************

useieee.std_logic_arith.all;

entityledctrlis 

endledctrl;

architectureoneofledctrlis

signalledon:

signalcount:

process（clk）is

ifrising_edge（clk）then 

ifcount="

thencount<

elsecount<

=count+1;

selo<

=count;

ledon<

=slwhencount="

else

'

&

shwhencount="

001"

mlwhencount="

010"

mhwhencount="

011"

hlwhencount="

100"

"

hhwhencount="

;

dp<

whencount="

orcount="

sego<

0111111"

whenledon="

0000110"

0001"

1011011"

0010"

1001111"

1100110"

0100"

1101101"

0101"

1111101"

0110"

0000111"

0111"

1111111"

1000"

1101111"

0000000"