微机原理课件ch10英文PPT文件格式下载.ppt

微机原理课件ch10英文PPT文件格式下载.ppt

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AddressDecoding,2023/5/4,第2页,MemoryDevices,TypeROM:

Read-onlymemoryRAM:

Read-WritememoryFourcommonlyusedmemoriesROMFlash,EEPROMStaticRAM（SRAM）DynamicRAM（DRAM）,SDRAM,RAMBUS,DDRRAMGenericpinconfiguration,2023/5/4,第3页,MemoryChip,AddressPinsThenumberofaddresspinsisrelatedtothenumberofmemorylocations1Mfor20pinsDataPinsThedatapinsaretypicallybi-directionalinread-writememories.Thenumberofdatapinsisrelatedtothesizeofthememorylocation.Forexample,an8-bitwide（byte-wide）memorydevicehas8datapins.Cataloglistingof1KX8indicateabyteaddressable8Kbitmemorywith10addresspins.ControlPins#CSor#S:

ChipSelect,enableread/writeoperations#OEor#G:

OutputEnable,enables/disablesasetoftri-statebuffers#WE:

writeenableSomechips,R/#W,2023/5/4,第4页,ROM,Non-volatilememory:

Maintainsitsstatewhenpowereddown.Thereareseveralforms:

ROM:

Factoryprogrammed,cannotbechanged.Olderstyle.PROM:

ProgrammableRead-OnlyMemory.Fieldprogrammablebutonlyonce.Olderstyle.EPROM:

ErasableProgrammableRead-OnlyMemory.Reprogrammingrequiresupto20minutesofhigh-intensityUVlightexposure.Flash,EEPROM:

ElectricallyErasableProgrammableROM.AlsocalledEAROM（ElectricallyAlterableROM）andNOVRAM（NOn-VolatileRAM）.WritingismuchslowerthananormalRAM.Usedtostoresetupinformation,e.g.videocard,oncomputersystems.CanbeusedtoreplaceEPROMforBIOSmemory.,2023/5/4,第5页,ROM,AddressBusDataBusControlBusChipEnable:

#CEOutputEnable:

#OE,2023/5/4,第6页,ReadOperation,2023/5/4,第7页,StandardEPROMICs,2023/5/4,第8页,Intel2716EPROM,2023/5/4,第9页,Intel2716EPROM,2023/5/4,第10页,RAM,2023/5/4,第11页,RAM,DRAMvsSRAMSRAMsarelimitedinsize.DRAMsareavailableinmuchlargersizes,e.g.,64M1.DRAMsMUSTberefreshed（rewritten）every2to4msSincetheystoretheirvalueonanintegratedcapacitorthatloseschargeovertime.ThisrefreshisperformedbyaspecialcircuitintheDRAMwhichrefreshestheentirememory.Refreshalsooccursonanormalreadorwrite.ThelargestoragecapacityofDRAMsmakeitimpracticaltoaddtherequirednumberofaddresspins.Instead,theaddresspinsaremultiplexed.,2023/5/4,第12页,RAM,2023/5/4,第13页,TI4016SRAM,2023/5/4,第14页,DRAM,TheTMS4464canstoreatotalof256Kbitsofdata.Ithas64Kaddressablelocationswhichmeansitneeds16addressinputs,butithasonly8.Therowaddress（A0throughA7）areplacedontheaddresspinsandstrobedintoasetofinternallatches.Thecolumnaddress（A8throughA15）isthenstrobedinusingCAS.,2023/5/4,第15页,DRAMTiming,2023/5/4,第16页,AddressDecoding,Theprocessorcanusuallyaddressamemoryspacethatismuchlargerthanthememoryspacecoveredbyanindividualmemorychip.Inordertospliceamemorydeviceintotheaddressspaceoftheprocessor,decodingisnecessary.Forexample,the8088issues20-bitaddressesforatotalof1MBofmemoryaddressspace.However,theBIOSona2716EPROMhasonly2KBofmemoryand11addresspins.Adecodercanbeusedtodecodetheadditional9addresspinsandallowtheEPROMtobeplacedinany2KBsectionofthe1MBaddressspace.,2023/5/4,第17页,AddressDecoding,2023/5/4,第18页,Todeterminetheaddressrangethatadeviceismappedinto:

This2KBmemorysegmentmapsintotheresetlocationofthe8086/8088（FFFF0H）.NANDgatedecodersarenotoftenusedLargefan-inNANDgatesarenotefficientMultipleNANDgateICsmightberequiredtoperformsuchdecodingRatherthe3-to-8LineDecoder（74LS138）ismorecommon.,AddressDecoding,2023/5/4,第19页,3-8LineDecoder74LS138,NotethatallthreeEnables（G2A,G2B,andG1）mustbeactive,e.g.low,lowandhigh,respectively.Eachoutputofthedecodercanbeattachedtoan2764EPROM（8K8）.,2023/5/4,第20页,Decodingwith74LS138,2023/5/4,第21页,8088/80188（8-bit）MemoryInterface,Thememorysystemsseesthe8088asadevicewith:

20addressconnections（A19toA0）.8databusconnections（AD7toAD0）.3controlsignals,IO/M,RD,andWR.Welllookatinterfacingthe8088with:

32KofEPROM（ataddressesF8000HthroughFFFFFH）.512KofSRAM（ataddresses00000Hthrough7FFFFH）.TheEPROMinterfaceusesa74LS138（3-to-8linedecoder）plus82732（4K8）EPROMs.,2023/5/4,第22页,8088/80188（8-bit）MemoryInterface,2023/5/4,第23页,8088/80188（8-bit）MemoryInterface,2023/5/4,第24页,8086-80386SX16-bitMemoryInterface,2023/5/4,第25页,8086-80386SX16-bitMemoryInterface,2023/5/4,第26页,8086-80386SX16-bitMemoryInterface,2023/5/4,第27页,MemoryInterface,2023/5/4,第28页,HardwareOrganizationoftheMemoryAddressSpace,2023/5/4,第29页,DataTransfer,8088,2023/5/4,第30页,DataTransfer,8086,2023/5/4,第31页,DataTransfer,8086,2023/5/4,第32页,DataTransfer,8086,2023/5/4,第33页,DataTransfer,8086,2023/5/4,第34页,MemoryArchitecture,2023/5/4,第35页,MemoryArchitecture,2023/5/4,第36页,MemoryArchitecture,2023/5/4,第37页,MemoryArchitecture,2023/5/4,第38页,MemoryConstructionProblems,Giventheaddressrange,howmanychipisneededtocontructthememoryspace?

Giventhespecificaddress,howtoarrangethememorychip?

Giventheconnectedmemorychipdiagram,howtocalculatetheaddressrange?

2023/5/4,第39页,Homework,2,3,7,19,22,27,31,2023/5/4,第40页,