AT89S52单片机外文翻译.docx
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AT89S52单片机外文翻译
英文原文及翻译
英文原文:
AT89S52
Features
•CompatiblewithMCS-51Products
•8KBytesofIn-SystemProgrammable(ISP)FlashMemory–Endurance:
10,000Write/EraseCycles
•4.0Vto5.5VOperatingRange
•FullyStaticOperation:
0Hzto33MHz
•Three-levelProgramMemoryLock
•256x8-bitInternalRAM
•32ProgrammableI/OLines
•Three16-bitTimer/Counters
•EightInterruptSources
•FullDuplexUARTSerialChannel
•Low-powerIdleandPower-downModes
•InterruptRecoveryfromPower-downMode
•WatchdogTimer•DualDataPointer
•Power-offFlag•FastProgrammingTime
•FlexibleISPProgramming(ByteandPageMode)
•Green(Pb/Halide-free)PackagingOption
1.Description
TheAT89S52isalow-power,high-performanceCMOS8-bitmicrocontrollerwith8Kbytesofin-systemprogrammableFlashmemory.ThedeviceismanufacturedusingAtmel’shigh-densitynonvolatilememorytechnologyandiscompatiblewiththeindus-try-standard80C51instructionsetandpinout.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememorypro-grammer.Bycombiningaversatile8-bitCPUwithin-systemprogrammableFlashonamonolithicchip,theAtmelAT89S52isapowerfulmicrocontrollerwhichprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplications.
TheAT89S52providesthefollowingstandardfeatures:
8KbytesofFlash,256bytesofRAM,32I/Olines,Watchdogtimer,twodatapointers,three16-bittimer/counters,asix-vectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillator,andclockcircuitry.Inaddition,theAT89S52isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialport,andinterruptsystemtocontinuefunctioning.ThePower-downmodesavestheRAMcon-tentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenextinterruptorhardwarereset.
2.PinDescription
VCC:
Supplyvoltage.
GND:
Ground.
Port0:
Port0isan8-bitopendrainbidirectionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashigh-impedanceinputs.Port0canalsobeconfiguredtobethemultiplexedlow-orderaddress/databusduringaccessestoexternalprogramanddatamemory.Inthismode,P0hasinternalpull-ups.Port0alsoreceivesthecodebytesduringFlashprogrammingandoutputsthecodebytesdur-ingprogramverification.Externalpull-upsarerequiredduringprogramverification.
Port1:
Port1isan8-bitbidirectionalI/Oportwithinternalpull-ups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pins,theyarepulledhighbytheinter-nalpull-upsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpull-ups.Inaddition,P1.0andP1.1canbeconfiguredtobethetimer/counter2externalcountinput(P1.0/T2)andthetimer/counter2triggerinput(P1.1/T2EX),respectively,asshowninthefollow-ingtable.
Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.
Table1
PortPin
AlternateFunctions
P1.0
T2(externalcountinputtoTimer/Counter2),clock-out
P1.1
T2EX(Timer/Counter2capture/reloadtriggeranddirectioncontrol)
P1.5
MOSI(usedforIn-SystemProgramming)
P1.6
MISO(usedforIn-SystemProgramming)
P1.7
SCK(usedforIn-SystemProgramming)
Port2:
Port2isan8-bitbidirectionalI/Oportwithinternalpull-ups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pins,theyarepulledhighbytheinter-nalpull-upsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpull-ups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryanddur-ingaccessestoexternaldatamemorythatuse16-bitaddresses(MOVX@DPTR).Inthisapplication,Port2usesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses(MOVX@RI),Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogram-mingandverification.
Port3:
Port3isan8-bitbidirectionalI/Oportwithinternalpull-ups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pins,theyarepulledhighbytheinter-nalpull-upsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseofthepull-ups.Port3receivessomecontrolsignalsforFlashprogrammingandverification.Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89S52,asshowninthefol-lowingtable.
Table2
PortPin
AlternateFunctions
P3.0
RXD(serialinputport)
P3.1
TXD(serialoutputport)
P3.2
(externalinterrupt0)
P3.3
(externalinterrupt1)
P3.4
T0(timer0externalinput)
P3.5
T1(timer1externalinput)
P3.6
(externaldatamemorywritestrobe)
P3.7
(externaldatamemoryreadstrobe)
RST:
Resetinput.Ahighonthispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedevice.Thispindriveshighfor98oscillatorperiodsaftertheWatchdogtimesout.TheDISRTObitinSFRAUXR(address8EH)canbeusedtodisablethisfeature.InthedefaultstateofbitDISRTO,theRESETHIGHoutfeatureisenabled.
ALE/
:
AddressLatchEnable(ALE)isanoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemory.Thispinisalsotheprogrampulseinput(
)duringFlashprogramming.Innormaloperation,ALEisemittedataconstantrateof1/6theoscillatorfrequencyandmaybeusedforexternaltimingorclockingpurposes.Note,however,thatoneALEpulseisskippeddur-ingeachaccesstoexternaldatamemory.Ifdesired,ALEoperationcanbedisabledbysettingbit0ofSFRlocation8EH.Withthebitset,ALEisactiveonlyduringaMOVXorMOVCinstruction.Otherwise,thepinisweaklypulledhigh.SettingtheALE-disablebithasnoeffectifthemicrocontrollerisinexternalexecutionmode.
:
ProgramStoreEnable(
)isthereadstrobetoexternalprogrammemory.WhentheAT89S52isexecutingcodefromexternalprogrammemory,
isactivatedtwiceeachmachinecycle,exceptthattwo
activationsareskippedduringeachaccesstoexter-naldatamemory.
/VPP:
ExternalAccessEnable.
mustbestrappedtoGNDinordertoenablethedevicetofetchcodefromexternalprogrammemorylocationsstartingat0000HuptoFFFFH.Note,however,thatiflockbit1isprogrammed,
willbeinternallylatchedonreset.
shouldbestrappedtoVCCforinternalprogramexecutions.Thispinalsoreceivesthe12-voltprogrammingenablevoltage(VPP)duringFlashprogramming.
XTAL1:
Inputtotheinvertingoscillatoramplifierandinputtotheinternalclockoperatingcircuit.
XTAL2:
Outputfromtheinvertingoscillatoramplifier.
3.MemoryOrganization
MCS-51deviceshaveaseparateaddressspaceforProgramandDataMemory.Upto64KbyteseachofexternalProgramandDataMemorycanbeaddressed.
3.1ProgramMemory
Ifthe
pinisconnectedtoGND,allprogramfetchesaredirectedtoexternalmemory.OntheAT89S52,if
isconnectedtoVCC,programfetchestoaddresses0000Hthrough1FFFHaredirectedtointernalmemoryandfetchestoaddresses2000HthroughFFFFHaretoexternalmemory.
3.2DataMemory
TheAT89S52implements256bytesofon-chipRAM.Theupper128bytesoccupyaparalleladdressspacetotheSpecialFunctionRegisters.Thismeansthattheupper128byteshavethesameaddressesastheSFRspacebutarephysicallyseparatefromSFRspace.Whenaninstructionaccessesaninternallocationaboveaddress7FH,theaddressmodeusedintheinstructionspecifieswhethertheCPUaccessestheupper128bytesofRAMortheSFRspace.InstructionswhichusedirectaddressingaccesstheSFRspace.Forexample,thefollowingdirectaddressinginstructionaccessestheSFRatlocation0A0H(whichisP2).
MOV0A0H,#data
Instructionsthatuseindirectaddressingaccesstheupper128bytesofRAM.Forexample,thefollowingindirectaddressinginstruction,whereR0contains0A0H,accessesthedatabyteataddress0A0H,ratherthanP2(whoseaddressis0A0H).
MOV@R0,#data
Notethatstackoperationsareexamplesofindirectaddressing,sotheupper128bytesofdataRAMareavailableasstackspace.
4.WatchdogTimer(One-timeEnabledwithReset-out)
TheWDTisintendedasarecoverymethodinsituationswheretheCPUmaybesubjectedtosoftwareupsets.TheWDTconsistsofa14-bitcounterandtheWatchdogTimerReset(WDTRST)SFR.TheWDTisdefaultedtodisablefromexitingreset.ToenabletheWDT,ausermustwrite01EHand0E1HinsequencetotheWDTRSTregister(SFRlocation0A6H).WhentheWDTisenabled,itwillincrementeverymachinecyclewhiletheoscillatorisrunning.TheWDTtimeoutperiodisdependentontheexternalclockfrequency.ThereisnowaytodisabletheWDTexceptthroughreset(eitherhardwareresetorWDToverflowreset).WhenWDTover-flows,itwilldriveanoutputRESETHIGHpulseattheRSTpin.
4.1UsingtheWDT
ToenabletheWDT,ausermustwrite01EHand0E1HinsequencetotheWDTRSTregister(SFRlocation0A6H).WhentheWDTisenabled,theuserneedstoserviceitbywriting01EHand0E1HtoWDTRSTtoavoidaWDToverflow.The14-bitcounteroverflowswhenitreaches16383(3FFFH),andthiswillresetthedevice.WhentheWDTisenabled,itwillincrementeverymachinecyclewhiletheoscilla