VHDL考试必备大全备课讲稿Word文件下载.docx
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1.设计一个异或门（采用行为描述方式）
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYxor2_v1IS
PORT（a,b:
INSTD_LOGIC;
y:
OUTSTD_LOGIC）;
ENDxor2_v1;
ARCHITECTUREbehaveOFxor2_v1IS
BEGIN
y<
=aXORb;
ENDbehave;
2.编写一个8线—3线编码器的VHDL程序（采用行为描述方式）
ENTITYcoder83_v1IS
PORT（I0,I1,I2,I3,I4,I5,I6,I7:
A0,A1,A2:
ENDcoder83_v1;
ARCHITECTUREbehaveOFcoder83_v1IS
BEGIN
A2<
=I4ORI5ORI6ORI7;
A1<
=I2ORI3ORI6ORI7;
A0<
=I1ORI3ORI5ORI7;
3.以74148逻辑表达式为依据，编写一个8线—3线优先编码器的VHDL程序（行为）
ENTITYprioritycoder83_v1IS
PORT（I7,I6,I5,I4,I3,I2,I1,I0:
EI:
INSTD_LOGIC;
A2,A1,A0:
OUTSTD_LOGIC;
GS,EO:
OUTSTD_LOGIC）;
ENDprioritycoder83_v1;
ARCHITECTUREbehaveOFprioritycoder83_v1IS
=EIOR（I7ANDI6ANDI5ANDI4）;
=EIOR（I7ANDI6ANDI3ANDI2）
OR（I7ANDI6ANDNOTI5）
OR（I7ANDI6ANDNOTI4）;
=EIOR（I7ANDNOTI6）
OR（I7ANDI5ANDNOTI4）
OR（I7ANDI5ANDI3ANDI1）
OR（I7ANDI5ANDI3ANDNOTI2）;
GS<
=EIOR（I7ANDI6ANDI5ANDI4ANDI3
ANDI2ANDI1ANDI0）;
EO<
=EIORNOT（I7ANDI6ANDI5
ANDI4ANDI3ANDI2ANDI1ANDI0）;
ENDbehave;
4.编写一个3线—8线译码器74138VHDL程序（数据流描述方式）
ENTITYdecoder138_v2IS
PORT（G1,G2A,G2B:
A:
INSTD_LOGIC_VECTOR（2DOWNTO0）;
Y:
OUTSTD_LOGIC_VECTOR（7DOWNTO0））;
ENDdecoder138_v2;
ARCHITECTUREdataflowOFdecoder138_v2IS
PROCESS（G1,G2A,G2B,A）
BEGIN
IF（G1='
1'
ANDG2A='
0'
ANDG2B='
）THEN
CASEAIS
WHEN"
000"
=>
Y<
="
11111110"
;
001"
11111101"
010"
11111011"
011"
11110111"
100"
11101111"
101"
11011111"
110"
10111111"
WHENOTHERS=>
01111111"
ENDCASE;
ELSEY<
11111111"
ENDIF;
ENDPROCESS;
ENDdataflow;
5.编写一个8选1数据选择器的VHDL程序（IF语句）
ENTITYmux8_v2IS
PORT（A:
INSTD_LOGIC_VECTOR（2DOWNTO0）;
D0,D1,D2,D3,D4,D5,D6,D7:
G:
YB:
ENDmux8_v2;
ARCHITECTUREdataflowOFmux8_v2IS
PROCESS（A,D0,D1,D2,D3,D4,D5,D6,D7,G）
IF（G='
）THEN
='
YB<
ELSIF（G='
ANDA="
）THEN
=D0;
=NOTD0;
=D1;
=NOTD1;
=D2;
=NOTD2;
ELSIF（G='
=D3;
=NOTD3;
=D4;
=NOTD4;
=D5;
=NOTD5;
=D6;
=NOTD6;
ELSE
=D7;
=NOTD7;
ENDdataflow;
6.编写一个对两个4位二进制数进行比较的程序（IF语句）
ENTITYcomp4_v1IS
INSTD_LOGIC_VECTOR（3DOWNTO0）;
B:
YA,YB,YC:
ENDcomp4_v1;
ARCHITECTUREbehaveOFcomp4_v1IS
PROCESS（A,B）
BEGIN
IF（A>
B）THEN
YA<
YC<
ELSIF（A<
B）THEN
7.编写一个用“+”实现加法运算的8位加法器的程序
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYadder8_vIS
PORT（A:
INSTD_LOGIC_VECTOR（7DOWNTO0）;
B:
Cin:
Co:
S:
OUTSTD_LOGIC_VECTOR（7DOWNTO0））;
ENDadder8_v;
ARCHITECTUREbehaveOFadder8_vIS
SIGNALSint:
STD_LOGIC_VECTOR（8DOWNTO0）;
SIGNALAA,BB:
AA<
&
A（7DOWNTO0）;
BB<
B（7DOWNTO0）;
Sint<
=AA+BB+Cin;
S（7DOWNTO0）<
=Sint（7DOWNTO0）;
Co<
=Sint（8）;
8.编写一个8求补器的程序。
libraryieee;
useieee.std_logic_1164.all;
entityhosuuis
port（a:
instd_logic_vector（7downto0）;
b:
outstd_logic_vector（7downto0））;
endhosuu;
architecturertlofhosuuis
begin
b<
=nota+‘1’;
endrtl;
9.编写一个三态门程序
entitytri_gateis
port（din,en:
instd_logic;
dout:
outstd_logic）;
endtri_gate;
architecturezasoftri_gateis
tri_gate:
process（din,en）
Begin
if（en=’1’）then
dout<
=din;
else
=’Z’;
endif;
endprocess;
endzas;
10.D触发器（带有异步置位复位功能）
ENTITYd_ffyIS
PORT（clk,d,set,reset:
q,qd:
OUTSTD_LOGIC）;
ENDd_ffy;
ARCHITECTUREaOFd_ffyIS
PROCESS（clk,set,reset）
IF（set='
ANDreset='
q<
qd<
ELSIF（set='
ELSIF（clk'
EVENTANDclk='
=d;
=NOTd;
ENDPROCESS;
ENDa;
11.jk触发器（带有异步置位复位功能）
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYjk_asr_ffIS
PORT（j,k,clk,set,res:
INSTD_LOGIC;
q,qb:
OUTSTD_LOGIC）;
ENDjk_asr_ff;
ARCHITECTUREbehaveOFjk_asr_ffIS
SIGNALq_temp:
STD_LOGIC;
signaljk_temp:
STD_LOGIC_VECTOR（1DOWNTO0）;
jk_temp<
=j&
k;
PROCESS（clk,set,res）
IFset='
THENq_temp<
='
ELSIFres='
THENq_temp<
ELSEIF（clk'
EVENTANDclk='
）THEN
CASEjk_tempIS
01"
q_temp<
10"
00"
=q_temp;
11"
=NOTq_temp;
WHENothers=>
X'
ENDCASE;
ENDIF;
ENDPROCESS;
q<
qb<
12.带有使能端的RS触发器
ENTITYRSlatchIS
PORT（r,s,en:
INBIT;
BUFFERBIT）;
ENDRSlatch;
ARCHITECTURErs_archiOFRSlatchIS
SIGNALs1,r1:
BIT;
s1<
=sNANDen;
r1<
=rNANDen;
qb<
=r1NANDq;
=s1NANDqb;
ENDrs_archi;
13.带异步置位/复位的通用寄存器
ENTITYregisternIS
GENERIC（n:
INTEGER:
=1）;
PORT（d:
INSTD_LOGIC_VECTOR（nDOWNTO0）;
clk,en,set,reset:
q:
BUFFERSTD_LOGIC_VECTOR（nDOWNTO0））;
ENDregistern;
ARCHITECTUREaOFregisternIS
PROCESS（clk,set,reset）
=（OTHERS=>
'
）;
IF（en='
q<
ELSEq<
=q;
ENDIF;
ENDPROCESS;
14.通用串入/并出移位寄存器
ENTITYshiftbIS
=2）;
PORT（d,clk:
BUFFERSTD_LOGIC_VECTOR（0TOn））;
ENDshiftb;
ARCHITECTUREaOFshiftbIS
COMPONENTd_ff
PORT（clk,d:
q:
ENDCOMPONENT;
label1:
FORiIN0TOnGENERATE
g1:
IF（i=0）GENERATE
dffx:
d_ffPORTMAP（clk=>
clk,d=>
d,q=>
q（i））;
ENDGENERATE;
g2:
IF（i/=0）GENERATE
q（i-1）,q=>
ENDGENERATE;
ARCHITECTUREaaOFshiftbIS
PROCESS（clk）
IF（clk'
q（0）<
FORiIN1TOnLOOP
q（i）<
=q（i-1）;
ENDLOOP;
ENDIF;
ENDaa;
15.循环移位寄存器
ENTITYshiftxIS
PORT（clk,load:
d:
INSTD_LOGIC_VECTOR（3DOWNTO0）;
OUTSTD_LOGIC_VECTOR（3DOWNTO0））;
ENDshiftx;
ARCHITECTUREaaOFshiftxIS
SIGNALtmp:
STD_LOGIC_VECTOR（3DOWNTO0）;
q<
=tmp;
IF（load='
tmp<
ELSEtmp（0）<
=tmp（3）;
tmp（3downto1）<
=tmp（2downto0）;
16.60进制递增计数器
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
ENTITYcntm60vIS
PORT（en:
INstd_logic;
clear:
load:
dl,dh:
INstd_logic_vector（3downto0）;
clk:
cout:
outstd_logic;
ql:
bufferstd_logic_vector（3downto0）;
qh:
bufferstd_logic_vector（3downto0））;
ENDcntm60v;
ARCHITECTUREbehaveOFcntm60vIS
signalent2:
std_logic;
PROCESS（clk）
VARIABLEtmpl,tmph:
std_logic_vector（3downto0）;
IF（clear='
tmpl:
0000"
tmph:
=“0000”;
--异步清零
ELSIF（clk'
EVENTANDclk='
）THEN
IFload='
THEN
=dl;
=dh;
--同步置数
elsif（en='
）then
if（tmpl="
1001"
--个位计数器9+1=0
if（tmph="
0101"
--十位计数器5+1=059+1=0
else
=tmph+1;
=tmpl+1;
endIF;
--endlf（load）
--endifclear
ql<
=tmpl;
ent2<
=tmpl（3）andtmpl（0）anden;
qh<
=tmph;
cout<
=tmph
（2）andtmph（0）andent2;
--计数器为59时进位信号cout输出‘1’。
ENDbehav
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