西南交大EDA期末报告Word格式文档下载.docx

西南交大EDA期末报告Word格式文档下载.docx

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ENDli_20112913_cipher_updown_5959_text;

ARCHITECTUREbdf_typeOFliu_20112910_cipher_updown_5959_textIS

SIGNALclk_100hz_clk_cnt10_0:

STD_LOGIC;

SIGNALclk_cnt10_1:

SIGNALclk_cnt10_2:

SIGNALclk_cnt10_4:

SIGNALclk_cnt6_3:

SIGNALclk_cnt6_5:

SIGNALseg7_m0:

STD_LOGIC_VECTOR（3DOWNTO0）;

SIGNALseg7_m1:

SIGNALseg7_m2:

SIGNALseg7_m3:

SIGNALseg7_m4:

SIGNALseg7_m5:

BEGIN

b2v_inst:

hsu_div_to_100

GENERICMAP（N=>

500000

）

PORTMAP（clk=>

clk,

outclk=>

clk_100hz_clk_cnt10_0）;

b2v_inst1:

hsu_count10_updown

PORTMAP（CLK=>

clk_100hz_clk_cnt10_0,

RST=>

res_in,

ENA=>

ena_in,

COUT=>

clk_cnt10_1,

OUTY=>

seg7_m0,

cipher=>

cipher_in）;

b2v_inst10:

hsu_2011am_seg7

PORTMAP（data_in=>

seg7_m3,

q_out=>

hex3）;

b2v_inst11:

seg7_m4,

hex4）;

b2v_inst12:

seg7_m5,

hex5）;

b2v_inst2:

clk_cnt10_2,

seg7_m1,

b2v_inst3:

clk_cnt6_3,

seg7_m2,

b2v_inst4:

hsu_count6_updown

clk_cnt10_4,

b2v_inst5:

clk_cnt6_5,

b2v_inst6:

cout_final,

b2v_inst7:

hex0）;

b2v_inst8:

hex1）;

b2v_inst9:

hex2）;

ENDbdf_type;

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_arith.all;

entityhsu_div_to_100is

GENERIC（N:

integer:

=500000）;

port（clk:

instd_logic;

outclk:

outstd_logic）;

endhsu_div_to_100;

architecturertlofhsu_div_to_100is

signalcount:

integer;

begin

process（clk）

begin

if（clk'

eventandclk='

1'

）then

if（count=N-1）then

count<

=0;

else

=count+1;

ifcount<

（integer（N/2））then

outclk<

='

0'

;

else

endif;

endif;

endprocess;

endrtl;

USEIEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITYhsu_count10_updownIS

PORT（CLK,RST,ENA:

INSTD_LOGIC;

OUTY:

OUTSTD_LOGIC_VECTOR（3DOWNTO0）;

COUT:

OUTSTD_LOGIC;

cipher:

INSTD_LOGIC_VECTOR（7DOWNTO0）

）;

ENDhsu_count10_updown;

ARCHITECTUREbehave_cnt10OFhsu_count10_updownIS

SIGNALCQI:

STD_LOGIC_VECTOR（3DOWNTO0）:

="

0000"

SIGNALflag1_2:

STD_LOGIC_VECTOR（1DOWNTO0）;

SIGNALcipher_temp:

STD_LOGIC_VECTOR（7DOWNTO0）;

cipher_temp<

=cipher;

P_COUNT10_VT:

PROCESS（CLK,RST,ENA,flag1_2）

BEGIN

IFRST='

THENCQI<

ELSIFCLK'

EVENTANDCLK='

THEN

IFENA='

if（flag1_2="

00"

IFCQI<

9THEN

CQI<

=CQI+1;

ELSE

ENDIF;

elsif（flag1_2="

01"

IFCQI>

0THEN

=CQI-1;

1001"

OUTY<

=CQI;

IF（flag1_2="

）THEN

COUT<

=NOT（CQI（3）ANDCQI（0））;

ELSIF（flag1_2="

=CQI（3）ORCQI

（2）ORCQI

（1）ORCQI（0）;

ENDPROCESSP_COUNT10_VT;

p1:

Process（clk,cipher_temp）

BEGIN

IF（clk'

EVENTANDclk='

IF（cipher_temp="

00001111"

flag1_2<

ELSIF（cipher_temp="

11110000"

11001100"

10"

ENDPROCESSp1;

p2:

Process（clk,flag1_2,CQI）

IF（flag1_2="

ENDPROCESSp2;

ENDbehave_cnt10;

ENTITYhsu_count6_updownIS

ENDhsu_count6_updown;

ARCHITECTUREbehave_cnt6OFhsu_count6_updownIS

STD_LOGIC_VECTOR（1DOWNTO0）;

STD_LOGIC_VECTOR（7DOWNTO0）;

cipher_temp<

PROCESS（CLK,RST,ENA）

5THEN

0101"

=NOT（CQI

（2）ANDCQI（0））;

ENDbehave_cnt6;

ENTITYhsu_2011am_seg7IS

PORT（data_in:

INSTD_LOGIC_VECTOR（3DOWNTO0）;

q_out:

OUTSTD_LOGIC_VECTOR（6DOWNTO0））;

ENDhsu_2011am_seg7;

ARCHITECTURErt1OFhsu_2011am_seg7IS

SIGNALtemp_data_in:

display_process:

PROCESS（data_in）

temp_data_in<

=data_in;

CASEtemp_data_inIS

WHEN"

=>

q_out<

="

1000000"

0001"

1111001"

0010"

0100100"

0011"

0110000"

0100"

0011001"

0010010"

0110"

0000010"

0111"

1111000"

1000"

0000000"

0010000"

1010"

0001000"

1011"

0000011"

1100"

1000110"

1101"

0100001"

1110"

0000110"

1111"

0001110"

WHENOTHERS=>

1111111"

ENDCASE;

ENDPROCESSdisplay_process;

ENDrt1;

C）sopc1

E）Hello

LIBRARYieee;

USEieee.std_logic_1164.all;

usework.li_20112913_hello_pkg.all;

ENTITYli_20112913_hello_topIS

（

clr:

clk:

OUTSTD_LOGIC_VECTOR（6DOWNTO0）

ENDli_20112913_hello_top;

ARCHITECTUREbdf_typeOFli_20112913_hello_topIS

SIGNALclk_1s:

SIGNALm0_to_hex0:

STD_LOGIC_VECTOR（2DOWNTO0）;

SIGNALm1_to_hex1:

SIGNALm2_to_hex2:

SIGNALm3_to_hex3:

SIGNALm4_to_hex4:

hsu_freqency_to_one_s

50000000

clk_1s）;

hsu_mux_3bit_5to1

PORTMAP（clk_5to1=>

clk_1s,

clr=>

clr,

m0=>

m0_to_hex0,

m1=>

m1_to_hex1,

m2=>

m2_to_hex2,

m3=>

m3_to_hex3,

m4=>

m4_to_hex4）;

hsu_seg7n_hello

m4_to_hex4,

data_hexn=>

entityhsu_seg7n_hellois

port（data_in:

instd_logic_vector（2downto0）;

data_hexn:

outstd_logic_vector（6downto0））;

endhsu_seg7n_hello;

architecturebehavior_seg7nofhsu_seg7n_hellois

begin

process（data_in）

casedata_inis

when"

000"

=>

data_hexn<

0001001"

001"

010"

1000111"

011"

whenothers=>

endcase;

endprocessp2;

endbehavior_seg7n;

entityhsu_mux_3bit_5to1is

port（clk_5to1,clr:

m4,m3,m2,m1,m0:

outstd_logic_vector（2downto0））;

endhsu_mux_3bit_5to1;

architecturebehavior_mux_3bit_5to1ofhsu_mux_3bit_5to1is

signalu:

std_logic_vector（2downto0）:

signalv: