大量的verilog源代码Word格式文档下载.docx

大量的verilog源代码Word格式文档下载.docx

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reg[7:

0]a;

0]b;

assignbidir=oe?

a:

8'

bZ;

assignoutp=b;

//AlwaysConstruct

always@（posedgeclk）

begin

b<

=bidir;

a<

=inp;

end

endmodule

多路选择器（MUX）

//

//-----------------------------------------------------------------------------------

//DESCRIPTION:

Multiplexer

//Codestyle:

usedcasestatement

//Widthofoutputterminal:

8

//Numberofterminals:

4

//Outputenableactive:

HIGH

//Outputvalueofallbitswhenenablenotactive:

0//-----------------------------------------------------------------------------------

modulemux（EN,IN0,IN1,IN2,IN3,SEL,OUT）;

inputEN;

0]IN0,IN1,IN2,IN3;

input[1:

0]SEL;

0]OUT;

always@（SELorENorIN0orIN1orIN2orIN3）

if（EN==0）OUT={8{1'

b0}};

else

case（SEL）

0:

OUT=IN0;

1:

OUT=IN1;

2:

OUT=IN2;

3:

OUT=IN3;

default:

OUT={8{1'

endcase

二进制到BCD码转换

BintoBcdconverter

//Input（data_in）width:

//Output（data_out）width:

//Enable（EN）active:

high

modulebin2bcd（data_in,EN,data_out）;

input[3:

0]data_in;

0]data_out;

always@（data_inorEN）

data_out={8{1'

if（EN==1）

case（data_in[3:

1]）

3'

b000:

data_out[7:

1]=7'

b0000000;

b001:

b0000001;

b010:

b0000010;

b011:

b0000011;

b100:

b0000100;

b101:

b0001000;

b110:

b0001001;

b111:

b0001010;

1]={7{1'

data_out[0]=data_in[0];

二进制到格雷码转换

//-----------------------------------------------------------------------------------//DESCRIPTION:

Bintograyconverter

//Input（DATA_IN）width:

//-----------------------------------------------------------------------------------moduleBIN2GARY（EN,DATA_IN,DATA_OUT）;

0]DATA_IN;

output[3:

0]DATA_OUT;

assignDATA_OUT[0]=（DATA_IN[0]^DATA_IN[1]）&

&

EN;

assignDATA_OUT[1]=（DATA_IN[1]^DATA_IN[2]）&

assignDATA_OUT[2]=（DATA_IN[2]^DATA_IN[3]）&

assignDATA_OUT[3]=DATA_IN[3]&

7段译码器

BINtosevensegmentsconverter

//segmentencoding

//a

//+---+

//f||b

//+---+<

-g

//e||c

//d

high//Outputs（data_out）active:

low//-----------------------------------------------------------------------------------

modulebin27seg（data_in,EN,data_out）;

output[6:

reg[6:

data_out=7'

b1111111;

case（data_in）

4'

b0000:

data_out=7'

b1000000;

//0

b0001:

b1111001;

//1

b0010:

b0100100;

//2

b0011:

b0110000;

//3

b0100:

b0011001;

//4

b0101:

b0010010;

//5

b0110:

//6

b0111:

b1111000;

//7

b1000:

//8

b1001:

b0011000;

//9

b1010:

//A

b1011:

//b

b1100:

b0100111;

//c

b1101:

b0100001;

//d

b1110:

b0000110;

//E

b1111:

b0001110;

//Fdefault:

二,基本时序逻辑功能:

8位数据锁存器

Flip-flopDtype

//Width:

//CLKactive:

//CLRactive:

//CLRtype:

synchronous

//SETactive:

//SETtype:

//LOADactive:

//CEactive:

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