电子综合设计多功能抢答器.docx
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电子综合设计多功能抢答器
电子综合设计
基于FPGA的四路智能抢答器
目录
1.设计目的
2.抢答器的特点
3.设计的内容要求
4.系统硬件原理图
5.软件流程图
6.系统电路图
7.系统各模块设计分析
8.原程序代码
9.设计感想
10.参考文献
11.附录
一、设计目的:
通过本次电子综合设计,掌握了数字电路系统的设计方法,进一步学会了如何使用数字电路实现现实的电路系统;学会了如何运用硬件描述语言VHDL驱动数字硬件电路的工作,实现软硬件连调,以达到软硬件协同工作的目的;加强自主动手制作硬件以及编程实现所需现实功能的能力;
二、抢答器的特点
抢答器是为智力竞赛参赛者答题时进行抢答而设计的一种优先判决器电路,广泛应用于各种知识竞赛、文娱活动等场合。
在各类竞赛中,特别是做抢答题时,在抢答过程中,为了知道哪一组或哪一名选手先答题,必须要有一个系统来完成这个任务。
抢答过程中,只靠人的视觉是很难判断出哪组先答题。
利用FPGA数字电路来设计抢答器,则可轻松解决这个问题。
够实现抢答器功能的方式有多种,可以采用模拟电路、数字电路或模拟与数字电路相结合的方式。
早期的抢答器只由几个三极管、可控硅、发光管等组成,能通过发光管的指示辨认出选手号码。
现在大多数抢答器均使用数字集成电路,并增加了许多新功能,如选手号码显示、抢按前或抢按后的计时、选手得分显示功能。
像这类抢答器,制作过程简单,准确性与可靠性高,而且安装维护简单。
随着电子技术的发展,现在的抢答器功能越来越强,可靠性和准确性也越来越高。
三、设计的内容要求:
1.设计一个智力抢答系统,可同时四名选手参加比赛,对应四个抢答按钮。
2.设置主持人控制键,包括开始、复位、加分、减分键。
3.倒计时系统,当主持人按开始键后,进行10s的倒计时抢答时间并在后5s开始蜂鸣报警,若无人抢答,开始下一题;若有选手抢答,该选手对应的指示灯熄灭,并进行30s的答题倒计时,并在后5s开始蜂鸣报警,由主持人加减选手的分,并开始下一题。
4.若违规操作,减一分。
四、系统硬件原理图
本次设计中使用了LB1板子上的资源有:
四个按键,4个led灯,6个数码管,蜂鸣器,芯片138,芯片244.
五、软件流程图
流程说明:
首先,下载程序后显示开机动画;当打开运行开关后,显示主界面,通过配置开关来控制LCD的分页。
LCD液晶屏主要显示五个分页,包括开机动画、组员和老师介绍、问题提问、分数显示及胜利选手恭喜界面。
而抢答器的控制流程具体如下,首先在开始时clear和start按键置低,准备比赛开始;选择题目,四组选手通过四个按键进行抢答。
抢答前有3秒准备时间,时间结束后开始抢答,否则视为犯规,自动扣一分;且抢答犯规者的LED灯闪亮,抢到者的LED灯常亮。
选手抢到后,有8秒的回答时间,通过小键盘输入选择答案,由裁判主持人进行答案的判断和加减分控制;如8秒结束后选手为作答,则自动扣一分,并显示出正确答案。
每轮问题结束后,自动统计每组选手和分数。
Clear按键按下,重新开始下一轮提问,start按键按下,开始抢答。
当比赛结束后,开关控制显示最高分者为胜出,有胜出界面,同时播放语音恭喜音乐。
六、系统电路图:
七、系统各模块设计分析:
1.分频模块
该模块对50MHZ的时钟分频,给其他模块提供相应的参考时钟,
2.去抖模块
由于机械按键会产生抖动,而抖动的上下沿在数字系统中比较敏感,容易产生毛刺甚至使系统产生无法预料的结果。
所以必须进行按键去抖。
仿真波形:
3.控制模块
仿真波形:
4.延迟模块
仿真波形:
5.蜂鸣器
该模块实现蜂鸣器报警提醒功能。
仿真波形:
6.显示模块
该模块为显示LED显示模块。
通过动态扫描同时显示几位LED。
其中输出led_a—led_g及dp段选,led_wei[5..0]为位选码,控制焊接的4个数码管来显示各组的分数,另外2个显示时间
仿真波形:
八、原程序代码:
1.分频模块:
libraryieee;
useIEEE.STD_LOGIC_1164.ALL;
ENTITYCLOCKIS
PORT(CLK_50MHz:
INSTD_LOGIC;
CLK_1MHZ:
OUTSTD_LOGIC;
CLK_2KHZ:
OUTSTD_LOGIC;
CLK_1KHZ:
OUTSTD_LOGIC;
CLK_100HZ:
OUTSTD_LOGIC;
CLK_5HZ:
OUTSTD_LOGIC;
CLK_1HZ:
OUTSTD_LOGIC
);
END;
ARCHITECTUREBEHAVOFCLOCKIS
SIGNALQ1,Q2,Q3,Q4,Q5,Q6:
STD_LOGIC;
SIGNALCOUNT1:
INTEGERRANGE25DOWNTO0;
SIGNALCOUNT2:
INTEGERRANGE12500DOWNTO0;
SIGNALCOUNT3:
INTEGERRANGE25000DOWNTO0;
SIGNALCOUNT4:
INTEGERRANGE250000DOWNTO0;
SIGNALCOUNT5:
INTEGERRANGE5000000DOWNTO0;
SIGNALCOUNT6:
INTEGERRANGE25000000DOWNTO0;
BEGIN
PROCESS(CLK_50MHz)
BEGIN
IFCLK_50MHz'EVENTANDCLK_50MHz='0'THEN
IFCOUNT1=24THEN
COUNT1<=0;
Q1<=NOTQ1;
ELSE
COUNT1<=COUNT1+1;
ENDIF;
------------------------------------------
IFCOUNT2=12499THEN
COUNT2<=0;
Q2<=NOTQ2;
ELSE
COUNT2<=COUNT2+1;
ENDIF;
------------------------------------------
IFCOUNT3=24999THEN
COUNT3<=0;
Q3<=NOTQ3;
ELSE
COUNT3<=COUNT3+1;
ENDIF;
------------------------------------------
IFCOUNT4=249999THEN
COUNT4<=0;
Q4<=NOTQ4;
ELSE
COUNT4<=COUNT4+1;
ENDIF;
------------------------------------------
IFCOUNT5=5999999THEN
COUNT5<=0;
Q5<=NOTQ5;
ELSE
COUNT5<=COUNT5+1;
ENDIF;
------------------------------------------
IFCOUNT6=25999999THEN
COUNT6<=0;
Q6<=NOTQ6;
ELSE
COUNT6<=COUNT6+1;
ENDIF;
ENDIF;
CLK_1MHZ<=Q1;
CLK_2KHZ<=Q2;
CLK_1KHZ<=Q3;
CLK_100HZ<=Q4;
CLK_5HZ<=Q5;
CLK_1HZ<=Q6;
ENDPROCESS;
ENDBEHAV;
2.去抖模块:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned;
entityshuruis
port(clk_1kHz:
instd_logic;
reset:
instd_logic;
start:
instd_logic;
sub:
instd_logic;
add:
instd_logic;
NUM1:
instd_logic;
NUM2:
instd_logic;
NUM3:
instd_logic;
NUM4:
instd_logic;
St:
outstd_logic;
Re:
outstd_logic;
AD:
outstd_logic;
Su:
outstd_logic;
NUM:
outstd_logic_vector(3downto0)
);
endentityshuru;
architecturebehavofshuruis
signalcount1,count2,count3,count4,count5,count6,count7,count8:
integerrange0to10000;
begin
process(clk_1kHz,reset,start,add,sub,NUM1,NUM2,NUM3,NUM4)
begin
ifclk_1kHz'eventandclk_1kHz='1'then
---------------------------------------------
ifstart='1'then
count1<=0;
else
count1<=count1+1;
endif;
ifcount1>20andcount1<70then
St<='0';
else
St<='1';
endif;
---------------------------------------------
ifreset='1'then
count2<=0;
else
count2<=count2+1;
endif;
ifcount2>20andcount2<70then
Re<='0';
else
Re<='1';
endif;
-------------------------------------------
ifadd='1'then
count3<=0;
else
count3<=count3+1;
endif;
ifcount3>20andcount3<70then
AD<='0';
else
AD<='1';
endif;
-----------------------------------------
ifsub='1'then
count4<=0;
else
count4<=count4+1;
endif;
ifcount4>20andcount4<70then
Su<='0';
else
Su<='1';
endif;
-----------------------------------------
ifNUM1='1'then
count5<=0;
else
count5<=count5+1;
endif;
ifcount5>20andcount5<70then
NUM(0)<='1';
else
NUM(0)<='0';
endif;
----------------------------------------
ifNUM2='1'then
count6<=0;
else
count6<=count6+1;
endif;
ifcount6>20andcount6<70then
NUM
(1)<='1';
else
NUM
(1)<='0';
endif;
----------------------------------------
ifNUM3='1'then
count7<=0;
else
count7<=count7+1;
endif;
ifcount7>20andcount7<70then
NUM
(2)<='1';
else
NUM
(2)<='0';
endif;
----------------------------------------
ifNUM4='1'then
count8<=0;
else
count8<=count8+1;
endif;
ifcount8>20andcount8<70then
NUM(3)<='1';
else
NUM(3)<='0';
endif;
---------------------------------------
endif;
endprocess;
endbehav;
3.控制模块:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYControlIS
PORT(START:
INSTD_LOGIC;
RESET:
INSTD_LOGIC;
ADD:
INSTD_LOGIC;
SUB:
INSTD_LOGIC;
NUM:
INSTD_LOGIC_VECTOR(3DOWNTO0);
OUT_TIME:
INSTD_LOGIC;
CLK_1MHz:
INSTD_LOGIC;
DEL_PRE:
OUTSTD_LOGIC;
DEL_ANS:
OUTSTD_LOGIC;
LED:
OUTSTD_LOGIC_VECTOR(3downto0);
SCORE1:
OUTSTD_LOGIC_VECTOR(3downto0);
SCORE2:
OUTSTD_LOGIC_VECTOR(3downto0);
SCORE3:
OUTSTD_LOGIC_VECTOR(3downto0);
SCORE4:
OUTSTD_LOGIC_VECTOR(3downto0)
);
END;
ARCHITECTUREBEHAVOFControlIS
TYPESTATEIS(S0,S1,S2);
SIGNALCURRENT_STATE,NEXT_STATE:
STATE;
SIGNALSCORE1_MID:
STD_LOGIC_VECTOR(3downto0);
SIGNALSCORE2_MID:
STD_LOGIC_VECTOR(3downto0);
SIGNALSCORE3_MID:
STD_LOGIC_VECTOR(3downto0);
SIGNALSCORE4_MID:
STD_LOGIC_VECTOR(3downto0);
SIGNALSCORE:
STD_LOGIC_VECTOR(3downto0);
SIGNALSCORE_ADD:
STD_LOGIC;
SIGNALSCORE_SUB:
STD_LOGIC;
SIGNALSCORE_CLK:
STD_LOGIC;
SIGNALNUM_STORE:
STD_LOGIC_VECTOR(3downto0);
BEGIN
-------------------------------------------------------------------
PROCESS(RESET,CLK_1MHz)
BEGIN
IFRESET='0'THEN
CURRENT_STATE<=S0;
ELSIFCLK_1MHz='1'ANDCLK_1MHz'EVENTTHEN
CURRENT_STATE<=NEXT_STATE;
ENDIF;
ENDPROCESS;
-------------------------------------------------------------------
PROCESS(CURRENT_STATE,NEXT_STATE,CLK_1MHz,NUM,START,OUT_TIME,ADD,SUB)
BEGIN
CASECURRENT_STATEIS
WHENS0=>DEL_PRE<='1';
DEL_ANS<='1';
LED<="0000";
SCORE_SUB<='0';
SCORE_ADD<='0';
IFSTART='0'THEN
NEXT_STATE<=S1;
ELSE
NEXT_STATE<=S0;
ENDIF;
WHENS1=>DEL_PRE<='0';
DEL_ANS<='1';
LED<="0000";
SCORE_SUB<='0';
SCORE_ADD<='0';
IFOUT_TIME='0'THEN
NEXT_STATE<=S0;
ELSIFNUM/="0000"THEN
NEXT_STATE<=S2;
NUM_STORE<=NUM;
ELSE
NEXT_STATE<=S1;
ENDIF;
WHENS2=>DEL_PRE<='1';
DEL_ANS<='0';
LED<=NUM_STORE;
IFOUT_TIME='0'THEN
SCORE_SUB<='1';
NEXT_STATE<=S0;
ELSIFSUB='0'THEN
SCORE_SUB<='1';
NEXT_STATE<=S0;
ELSIFADD='0'THEN
SCORE_ADD<='1';
NEXT_STATE<=S0;
ELSE
NEXT_STATE<=S2;
ENDIF;
ENDCASE;
ENDPROCESS;
PROCESS(SCORE_SUB,SCORE_ADD)
BEGIN
SCORE_CLK<=(SCORE_ADDORSCORE_SUB);
IFSCORE_CLK='1'ANDSCORE_CLK'EVENTTHEN
IFSCORE_ADD='1'THEN
IFNUM_STORE(0)='1'THEN
SCORE1_MID<=SCORE1_MID+'1';
ELSIFNUM_STORE
(1)='1'THEN
SCORE2_MID<=SCORE2_MID+'1';
ELSIFNUM_STORE
(2)='1'THEN
SCORE3_MID<=SCORE3_MID+'1';
ELSIFNUM_STORE(3)='1'THEN
SCORE4_MID<=SCORE4_MID+'1';
ENDIF;
ELSIFSCORE_SUB='1'THEN
IFNUM_STORE(0)='1'THEN
SCORE1_MID<=SCORE1_MID-'1';
ELSIFNUM_STORE
(1)='1'THEN
SCORE2_MID<=SCORE2_MID-'1';
ELSIFNUM_STORE
(2)='1'THEN
SCORE3_MID<=SCORE3_MID-'1';
ELSIFNUM_STORE(3)='1'THEN
SCORE4_MID<=SCORE4_MID-'1';
ENDIF;
ENDIF;
ENDIF;
SCORE1<=SCORE1_MID;
SCORE2<=SCORE2_MID;
SCORE3<=SCORE3_MID;
SCORE4<=SCORE4_MID;
ENDPROCESS;
ENDBEHAV;
4.延迟模块:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYDELAYIS
PORT(DEL_PRE:
INSTD_LOGIC;
DEL_ANS:
INSTD_LOGIC;--GAODIANPINSHIXIANSHIWEI00,DIDIANPINXIANSHIYIMIAODEYANSHI;
CLK_100Hz:
INSTD_LOGIC;
--CLK_1Hz:
OUTSTD_LOGIC;
OUT_TIME:
OUTSTD_LOGIC;
TIME1:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
TIME10:
OUTSTD_LOGIC_VECTOR(3DOWNTO0)
);
END;
ARCHITECTUREBEHAVOFDELAYIS
SIGNALCLK_1Hz_PRE:
STD_LOGIC;
SIGNALCLK_1Hz_ANS:
STD_LOGIC;
SIGNALCOUNT_PRE:
INTEGERRANGE0TO100;
SIGNALCOUNT_ANS:
INTEGERRANGE0TO100;
SIGNALOUT_TIME_PRE:
STD_LOGIC;
SIGNALOUT_TIME_ANS:
STD_LOGIC;
SIGNALCOUNT1_PRE,COUNT10_PRE:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALCOUNT1_ANS,COUNT10_ANS:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
PROCESS(CLK_100Hz)
BEGIN
IFDEL_PRE='0'THEN
IFCLK_100Hz'EVENTANDCLK_100Hz='1'THEN
IFCOUNT_PRE=99THEN
COUNT_PRE<=0;
CLK_1Hz_PRE<='1';
ELSE
COUNT_PRE<=COUNT_PRE+1;
CLK_1Hz_PRE<='0';
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
---------------------------------------------------------
PROCESS(CLK_100Hz)
BEGIN
IFDEL_ANS='0'THEN
IFCLK_100Hz'EVENTANDCLK_100Hz='1'THEN
IFCOUNT_ANS=99THEN
COUNT_ANS<=0;
CLK_1Hz_ANS<='1';
ELSE
COUNT_ANS<=COUNT_ANS+1;
CLK_1Hz_ANS<='0';
ENDIF;
ENDIF;
ENDIF;
END