完整word版EDA常见实例源程序代码vhdl.docx
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完整word版EDA常见实例源程序代码vhdl
第4章用VHDL程序实现常用逻辑电路
4.1组合逻辑电路设计
4.1.1基本逻辑门libraryieee;
useiee.std_logic_1164.all;
entityjbmis
port（a,b:
inbit;
f1,f2,f3,f4,f5,f:
outbit）;
endjbm;
architectureaofjbmis
begin
f1<=aandb;--构成与门
f2<=aorb;--构成或门
f<=nota;--构成非门
f3<=anandb;--构成与非门
f4<=anorb;--构成异或门
f5<=not（axorb）;--构成异或非门即同门end;
4.1.2三态门
libraryieee;
useieee.std_logic_1164.all;
entitytri_sis
port（enable:
instd_logic;
datain:
instd_logic_vector（7downto0）;dataout:
outstd_logic_vector（7downto0））;endtri_s;
architecturebhvoftri_sis
begin
process（enable,datain）
begin
ifenable='1'thendataout<=datain;
else
dataout<="ZZZZZZZZ";
endif;
endprocess;
endbhv;
4.1.33-8译码器
libraryieee;
useieee.std_logic_1164.all;
entitydecoder3_8is
port（a,b,c,g1,g2a,g2b:
instd_logic;
y:
outstd_logic_vector（7downto0））;
enddecoder3_8;
architectureaofdecoder3_8is
signaldz:
std_logic_vector（2downto0）;
begin
dz<=c&b&a;
process（dz,g1,g2a,g2b）
begin
if（g1='1'andg2a='0'andg2b='0'）thencasedzis
when"111"=>y<="01111111";whenothers=>y<="XXXXXXXX";endcase;
else
endif;
endprocess;
4.1.4优先编码器
libraryieee;
useieee.std_logic_1164.all
entitycoderis
port（din:
instd_logic_vector（0to7）;
output:
outstd_logic_vector（0to2））;
endcoder;
architecturebehaveofcoderis
signalsint:
std_logic_vevtor（4downto0）;
begin
process（din）
begin
if（din（7）='0'）thenoutput<="000";
elsif（din（6）='0'）thenoutput<="100";
elsif（din（5）='0'）thenoutput<="010";
elsif（din（4）='0'）thenoutput<="110";
elsif（din（3）='0'）thenoutput<="001";
elsif（din
（2）='0'）thenoutput<="101";
elsif（din
（1）='0'）then
output<="011";
else
output<="111";
endif;
endprocess;
endbehav;
4.1.57段码译码器
libraryieee;
useieee.std_logic_1164.all
entitydecl7sis
port（a:
instd_logic_vector（3downto0）;led7s:
outstd_logic_vector（6downto0））;
enddecl7s;
architecturebehaveofdecl7sis
begin
process（a）
begin
caseais
when"0000"=>led7s<="0111111";
when"0001"=>led7s<="0000110";
led7s<="1011011"led7s<="1001111"led7s<="1100110"led7s<="1101101"led7s<="1111101"led7s<="0000111"led7s<="1111111"led7s<="1101111"led7s<="1110111"led7s<="1111100"led7s<="0111001"led7s<="1011110"led7s<="1111001"led7s<="1110001"null;
when"0010"=>
when"0011"=>
when"0100"=>
when"0101"=>
when"0110"=>
when"0111"=>
when"1000"=>
when"1001"=>
when"1010"=>
when"1011"=>
when"1100"=>
when"1101"=>
when"1110"=>
when"1111"=>whenothers=>endcase;
endprocess;endbehave;
4.1.6二-十进制BCD译码器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_signed.all;
entitybcdymqis
port（din:
inintegerrange15downto0;
a,b:
outintegerrange9downto0）;end;
architecturefpq1ofbcdymqis
begin
p1:
process（din）
beginifdin<10then
a<=din;b<=0;
else
a<=din-10;
b<=1;
endif;
endprocessp1;
end;
4.1.7多位加（减）法器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_signed.all;
entityjianfaqiis
port（a,b:
instd_logic_vector（0to3）;c0:
instd_logic;c1:
outstd_logic;
d:
outstd_logic_vector（0to3））;
end;
architectureaofjianfaqiis
begin
process
begin
ifa>b+c0thend<=a-（b+c0）;c1<='0';
else
c1<='1';d<=（"10000"）-（b+c0-a）;endif;
endprocess;
end;
4.2时序逻辑电路设计
4.2.1触发器
RS触发器
libraryieee;
useieee.std_logic_1164.all;useieee.std_logic_signed.all;entityrsffisport（r,s,clk:
instd_logic;
q,qb:
bufferstd_logic）;endrsff;
architecturersff_artofrsffissignalq_s,qb_s:
std_logic;
beginprocess（clk,r,s）begin
if（clk'eventandclk='1'）then
if（s='1'andr='0'）then
q_s<='0';
qb_s<='1';
elsif（s='0'andr='1'）thenq_s<='1';qb_s<='0';
elsif（s='0'andr='0'）thenq_s<=q_s;qb_s<=qb_s;
endif;
endif;
q_s<=q_s;qb_s<=qb_s;
endprocess;
endrsff_art;
同步复位D触发器
libraryieee;
useieee.std_logic_1164.all;useieee.std_logic_signed.all;entitysyndffisport（d,clk,reset:
instd_logic;
q,qb:
outstd_logic）;endsyndff;architecturedff_artofsyndffisbeginprocess（clk）begin
if（clk'eventandclk='1'）thenif（reset='0'）thenq<='0';qb<='1';
else
q<=d;
qb<=notq;endif;endif;
endprocess;
enddff_art;
JK触发器
libraryieee;
useieee.std_logic_1164.all;useieee.std_logic_signed.all;entityasynjkffisport（j,k,clk,set.reset:
instd_logic;q,qb:
outstd_logic）;
endasynjkff;
architecturejkff_artofasynjkffissingalq_s,qb_s:
std_logic;
beginprocess（clk,set,reset）begin
if（set='0'andreset='1'）thenq_s<='1';qb_s<='0';
elsif（set='1'andreset='0'）then
q_s<='0';
qb_s<='1';
elsif（clk'eventandclk='1'）thenif（j='0'andk='1'）thenq_s<='0';qb_s<='1';
elsif（j='1'andk='0'）thenq_s<='1';qb_s<='0';
elsif（j='1'andk='1'）thenq_s<=notq_s;qb_s<=notqb_s;
endif;
endif;q<=q_s;qb<=qb_s;
endprocess;
endjkff_art;
T触发器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_signed.all;
entitytffis
port（t,clk:
instd_logic;q:
outstd_logic）;
end;architecturetff_artoftffissignalq_temp:
std_logic;
beginp1:
process（clk）beginifrising_edge（clk）thenift='1'then
q_temp<=notq_temp;else
q_temp<=q_temp;
endif;
endif;
q<=q_temp;
endprocess;q<=q_temp;
endtff_art;
4.2.2计数器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycnt4IS
port（clk:
instd_logic;
q:
outstd_logic_vector（3downto0））;
endcnt4;
architecturebehaveofcnt4is
signalq1:
std_logic_vector（3downto0）;begin
process（clk）
begin
if（clk'eventandclk='1'）thenq1<=q1+1;
endif;
endprocess;
q<=q1;
endbehave;
般计数器设计
libraryieee;
useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycnt10is
endcnt10;
architecturebehaveofcnt10isbegin
process（clk,rst,en,updown）variablecqi:
std_logic_vector（3downto0）;
endbehave;
4.2.3分频器libraryieee;usestd_logic_1164.all;usestd_logic_unsigned.all;
entityfreq1is
port（clk:
instd_logic;
d:
instd_logic_vector（7downto0）;fout:
outstd_logic）;
end;architectureoneofdvfis
signalfull:
std_logic;beginp_reg:
process（clk）
variablecnt8:
std_logic_vector（7downto0）;
begin
--检测时钟上升沿
ifclk'eventandclk='1'then
ifcnt8=''''thencnt8:
=d;full<='1';
elsecnt8:
=cnt8+1;full<='0';
endif;
endif;
endprocessp_reg;
p_div:
process（full）
variablecnt2:
std_logic;
begin
iffull'eventandfull='1'thencnt2:
=notcnt2;
ifcnt2='1'then
fout<='1';
else
fout<='0';
endif;
endif;
endprocessp_div;end;
4.2.4移位寄存器libraryieee;useieee.std_logic_1164.all;
--当CNT8计数计满时，输入数据D被同步预置给计数器
--同时使溢出标志信号FULL输出为高电平
--否则继续作加1计数
--且输出溢出标志信号FULL为低电平
--如果溢出标志信号FULL为高电平，T触发器输出取反
CNT8
entityshiftis
port（clk,c0:
instd_logic;--时钟和进位输入
md:
instd_logic_vector（2downto0）;--移位模式控制字d:
instd_logic_vector（7downto0）;--待加载移位的数据qb:
outstd_logic_vector（7downto0）;--移位数据输出cn:
outstd_logic）;--进位输出
end;
architecturebehaveofshiftis
signalreg:
std_logic_vector（7downto0）;signalcy:
std_logic;
begin
process（clk,md,c0）
begin
ifclk'eventandclk='1'then
casemdis
libraryieee;
useieee.std_logic_1164.all;
entitys_machineis
port（clk,reset:
instd_logic;
state_inputs:
instd_logic_vector（0to1）;comb_outputs:
outintegerrange0to15）;ends_machine;
whens0=>comb_outputs<=5;ifstate_inputs="00"thennext_state<=s0;
else
next_state<=s1;
endif;
whens1=>comb_outputs<=8;ifstate_inputs="00"thennext_state<=s1;
else
next_state<=s2;
endif;
whens2=>comb_outputs<=12;ifstate_inputs="11"thennext_state<=s0;
else
next_state<=s3;
endif;
whens3=>comb_outputs<=14;ifstate_inputs="11"thennext_state<=s3;
else
next_state<=s0;
endif;
endcase;
endprocess;
endbehv;
4.3.2状态机的应用libraryieee;useieee.std_logic_1164.all;entityasm_ledis
port（clk,clr:
instd_logic;
led1,led2,led3:
outstd_logic）;
end;
architectureaofasm_ledis
typestatesis（s0,s1,s2,s3,s4,s5）;--对状态机的状态声明
signalq:
std_logic_vector（0to2）;
signalstate:
states;
begin
p1:
process（clk,clr）
begin
if（clr='0'）then
state<=s0;
elsif（clk'eventandclk='1'）thencasestateiswhens0=>state<=s1;whens1=>state<=s2;whens2=>state<=s3;whens3=>state<=s4;whens4=>state<=s5;whens5=>state<=s0;whenothers=>state<=s0;
endcase;
endif;
endprocessp1;
p2:
process（clr,state）
begin
if（clr='0'）then
led1<='0';
led2<='0';led3<='0';
else
casestateis
whens0=>led1<='1';led2<='0';led3<='0';
whens1=>led1<='0';led2<='1';led3<='0';whens2=>led1<='0';led2<='1';led3<='0';whens3=>led1<='0';led2<='0';led3<='1';whens4=>led1<='0';led2<='0';led3<='1';whens5=>led1<='0';led2<='0';led3<='1';whenothers=>null;
endcase;endif;
endprocessp2;
end;
第6章EDA仿真技术应用实例6.1带使能和片选端的16：
4线优先编码器设计子模块设计源代码：
libraryieee;
useieee.std_logic_1164.all;
entitypencoderis
port（d:
instd_logic_vector（7downto0）;ei:
instd_logic;--ei:
enableinput
gs,eo:
outbit;--gs:
chipselectoutput;eo:
enableoutput
q2,q1,q0:
outstd_logic）;
endpencoder;
architectureencoderofpencoderisbegin
process（d）
beginif（d（0）='0'andei='0'）thenq2<='1';q1<='1';q0<='1';gs<='0';eo<='1';
elsif（d
（1）='0'andei='0'）thenq2<='1';q1<='1';q0<='0';gs<='0';eo<='1';
elsif（d
（2）='0'andei='0'）thenq2<='1';q1<='0';q0<='1';gs<='0';eo<='1';
elsif（d（3）='0'andei='0'）thenq2<='1';q1<='0';q0<='0';gs<='0';eo<='1';
elsif（d（4）='0'andei='0'）thenq2<='0';q1<='1';q0<='1';gs<='0';eo<='1';
elsif（d（5）='0'andei='0'）thenq2<='0';q1<='1';q0<='0';gs<='0';eo<='1';
elsif（d（6）='0'andei='0'）thenq2<='0';q1<='0';q0<='1';gs<='0';eo<='1';
elsif（d（7）='0'andei='0'）then--d7priotyencoder
q2<='0';q1<='0';q0<='0';
gs<='0';eo<='1';elsif（ei='1'）then
q2<='1';q1<='0';q0<='1';gs<='1';eo<='1';
'0'）t
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