国际学术会议海报模板20-academic_conference_poster_modelPPT资料.ppt

1、Best case 3D（Arch 3/WI）performs 12%better than best case 2D（Replicated Cache banks）.Better thermal profile:#Best case（Arch 3/WI）has just 10 0 C increase from 2D with maximum performance gains,Understanding the Impacts of 3D Stacked Layouts on ILPVivek Venkatesan,Manu Awasthi,Rajeev BalasubramonianSc

2、hool of Computing,University of Utah,Interconnects within a processor pipeline are known to be a major bottleneck for performance and power in future processors.Wire delays are Vertical 3D stacking of dies allows reduction of overall wire-lengths and helps alleviate the performance and power overhea

3、d of on-chip wiring.The primary disadvantage is that it results in increased power-densities and on-chip temperatures.,Floor-planning generates arbitrary layouts of micro-architectural blocks in a processor evaluating each with respect to an objective function Include delay-criticality information i

4、n the objective function to keep heavily communicating blocks closer 3D floor-planning generates 3D layouts,more potential to exploit closeness in the vertical dimension,Wire-latencies predicted to be in 10s of cycles in future fabrication technologies Studying the impact of wire-delays on performan

5、ce reinforces the need for interconnect optimization techniques Popular belief:#Multi-threading hides wire-delays,not entirely true!#Technique to alleviate key wire-delays-Floor-planning,BACKGROUND,IMPACT OF WIRE DELAYS,FLOOR-PLANNING,3D Technology has the potential to improve processor performance,

6、power and cost3D wafer bonding traps heat resulting in higher peak and average temperaturesTiled-architectures with long inter-cluster wires stand to gain more from 3D stackingAggressive cooling capabilities may be required to extract the full potential of 3DOther promising applications of 3D techno

7、logy include“snap-on”analysis engines,fault-correction engines and stacked memories.,CONCLUSIONS,3D TECHNOLOGY,3D Folding Proposed by Puttaswamy et.Al.,Drawback:#Increased Thermal Density,RegFile,Break and Stack,Proposed Solution:#3D Stacking,Arch 1,Arch 2,Arch 3,Cache Bank（Replicated/Word Interleaved）,Cluster,Observation:#Wire-Delay Limited Architectures stand to benefit more from a 3D integration technology,Reduced Wire Delays and Better Thermal Density!#,3D BENEFITS,2D Performance Comparison,Best Case 3D Performance,