国际学术会议海报模板20-academic_conference_poster_modelPPT资料.ppt

国际学术会议海报模板20-academic_conference_poster_modelPPT资料.ppt

《国际学术会议海报模板20-academic_conference_poster_modelPPT资料.ppt》由会员分享，可在线阅读，更多相关《国际学术会议海报模板20-academic_conference_poster_modelPPT资料.ppt（1页珍藏版）》请在冰点文库上搜索。

Bestcase3D（Arch3/WI）performs12%betterthanbestcase2D（ReplicatedCachebanks）.Betterthermalprofile:

@#@Bestcase（Arch3/WI）hasjust100Cincreasefrom2Dwithmaximumperformancegains,UnderstandingtheImpactsof3DStackedLayoutsonILPVivekVenkatesan,ManuAwasthi,RajeevBalasubramonianSchoolofComputing,UniversityofUtah,Interconnectswithinaprocessorpipelineareknowntobeamajorbottleneckforperformanceandpowerinfutureprocessors.WiredelaysareVertical3Dstackingofdiesallowsreductionofoverallwire-lengthsandhelpsalleviatetheperformanceandpoweroverheadofon-chipwiring.Theprimarydisadvantageisthatitresultsinincreasedpower-densitiesandon-chiptemperatures.,Floor-planninggeneratesarbitrarylayoutsofmicro-architecturalblocksinaprocessorevaluatingeachwithrespecttoanobjectivefunctionIncludedelay-criticalityinformationintheobjectivefunctiontokeepheavilycommunicatingblockscloser3Dfloor-planninggenerates3Dlayouts,morepotentialtoexploitclosenessintheverticaldimension,Wire-latenciespredictedtobein10sofcyclesinfuturefabricationtechnologiesStudyingtheimpactofwire-delaysonperformancereinforcestheneedforinterconnectoptimizationtechniquesPopularbelief:

@#@Multi-threadinghideswire-delays,notentirelytrue!

@#@Techniquetoalleviatekeywire-delays-Floor-planning,BACKGROUND,IMPACTOFWIREDELAYS,FLOOR-PLANNING,3DTechnologyhasthepotentialtoimproveprocessorperformance,powerandcost3DwaferbondingtrapsheatresultinginhigherpeakandaveragetemperaturesTiled-architectureswithlonginter-clusterwiresstandtogainmorefrom3DstackingAggressivecoolingcapabilitiesmayberequiredtoextractthefullpotentialof3DOtherpromisingapplicationsof3Dtechnologyinclude“snap-on”analysisengines,fault-correctionenginesandstackedmemories.,CONCLUSIONS,3DTECHNOLOGY,3DFoldingProposedbyPuttaswamyet.Al.,Drawback:

@#@IncreasedThermalDensity,RegFile,BreakandStack,ProposedSolution:

@#@3DStacking,Arch1,Arch2,Arch3,CacheBank（Replicated/WordInterleaved）,Cluster,Observation:

@#@Wire-DelayLimitedArchitecturesstandtobenefitmorefroma3Dintegrationtechnology,ReducedWireDelaysandBetterThermalDensity!

@#@,3DBENEFITS,2DPerformanceComparison,BestCase3DPerformance,