西安邮电学院数电eda实验 仿真.docx

1、西安邮电学院数电eda实验 仿真实验五：一、译码真值表Library ieee;Use ieee.std_logic_1164.all;Entity qiduan isPort(a:in std_logic_vector(3 downto 0); y:out std_logic_vector(6 downto 0);End;Architecture rtl of qiduan is BeginProcess(A)BeginCase A is When0000=yyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyy=ZZZZZZZ; End case;End process; En

2、d; 实验六一、RS触发器Library ieee;Use ieee.std_logic_1164.all;Entity rsff1 isPort(r,s,cp:in bit; q,qb:buffer bit);End;Architecture rtl of rsff1 isBeginqb=(r nand cp) nand q;q=(s nand cp) nand qb;End; 二、JK触发器Library ieee;Use ieee.std_logic_1164.all;Entity jkff1 isPort(j,k,clk,PRN,CLRN:in std_logic; q,qb:out

3、std_logic);End;Architecture rtl of jkff1 issignal q_temp,qb_temp:std_logic;BeginProcess(clk,PRN,CLRN) Begin if(PRN and CLRN )=0)then q_temp=not PRN; qb_temp=PRN; elsif ( clkevent and clk=1)then q_temp =(j and (not q_temp) or (not k and q_temp); qb_temp =not q_temp; end if; end process; q=q_temp; qb=

4、qb_temp;End;三、D触发器Library ieee;Use ieee.std_logic_1164.all;Entity dff1 isPort(d,clk,PRN,CLRN:in std_logic; q,qb:out std_logic);End;Architecture rtl of dff1 issignal q_temp,qb_temp:std_logic;BeginProcess(clk,PRN,CLRN)Begin if(PRN and CLRN )=0)then q_temp=not PRN; qb_temp=PRN; elsif ( clkevent and clk

5、=1)then q_temp =d; qb_temp =not q_temp; else q_temp=q_temp; end if;end process; q=q_temp; qb=qb_temp;End;四、开关控制电路设计题3.19的真值表A B C Y A B C Y0 0 0 0 0 1 1 00 0 1 1 1 0 1 00 1 0 1 1 1 0 01 0 0 1 1 1 1 1Library ieee;Use ieee.std_logic_1164.all;Entity kaiguan isPort(A,B,C:in std_logic;Y:out std_logic);En

6、d;Architecture rtl of kaiguan issignal D,f0:std_logic;BeginD=A or B or C;Process(D) Beginif(Devent and D=1)then f0=not f0;end if;End process;Y=f0; End; 实验七：一、设计一位四位带异步清零的并入串出移位寄存器LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY piso ISPORT(DATA_IN :IN STD_LOGIC_VECTOR(3 DOWNTO 0);CLK :IN STD_LOGIC;nL

7、OAD :IN STD_LOGIC;DATA_OUT :OUT STD_LOGIC);END piso;ARCHITECTURE a OF piso ISSIGNAL Q: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(nLOAD,CLK)BEGINIF nLOAD = 0 THENQ = DATA_IN;ELSIF CLKEVENT AND CLK = 1 THENq(1) = Q(0) ;FOR I IN 1 TO 3 LOOPQ(I) = Q(I-1);ENDLOOP;END IF;END PROCESS;PROCESS(nLOAD,CLK)BEGI

8、NIF nLOAD = 0 THENDATA_OUT = 0;ELSIF CLKEVENT AND CLK = 1 THENDATA_OUT = Q(3);END IF;END PROCESS;END a;二、环形计数器library IEEE;use IEEE.std_logic_1164.all;entity huanxing is port ( clk : in std_logic; load : in std_logic; d : in std_logic_vector(3 downto 0); q : out std_logic_vector(3 downto 0);end;arch

9、itecture shft_reg_arch of huanxing issignal TEMP : std_logic_vector(3 downto 0);beginprocess(clk) begin if clkevent and clk=1 then if load = 1 then TEMP = d; elsif TEMP=1000 then TEMP= TEMP(0) & TEMP(3 downto 1); elsif TEMP=0100 then TEMP= TEMP(0) & TEMP(3 downto 1); elsif TEMP=0010 then TEMP= TEMP(

10、0) & TEMP(3 downto 1); elsif TEMP=0001 then TEMP= TEMP(0) & TEMP(3 downto 1); else TEMP=1000; end if; end if; end process; q = TEMP;end architecture;真值表：CLKQ1000010000100001三、8位循环移位寄存器其中D表示输入的初始值，Sta为开始移位信号，DOUT表示当前数值；LD表示预设计数值，LD为“1”，初始计数值打入器件；LR表示移位方向，LR为0，循环右移位，LR为1，循环左移位；CP为移位脉冲。LIBRARY IEEE;USE

11、 IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY cyreg IS PORT(D : IN STD_LOGIC_VECTOR(7 DOWNTO 0); LD : IN STD_LOGIC; LR : IN STD_LOGIC; CP : IN STD_LOGIC; DOUT: BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0);END cyreg;ARCHITECTURE sample OF cyreg IS BEGIN P1:PROCESS(CP,LD) BEGIN if LD=0 then D

12、OUT=D; elsif CPEVENT AND CP=0 then if LR=1 then DOUT=DOUT(6 DOWNTO 0)&DOUT(7); elsif LR=0 then DOUT=DOUT(0)&DOUT(7 DOWNTO 1); end if; end if; END PROCESS P1; END sample;四、节日彩灯library IEEE;use IEEE.std_logic_1164.all;entity caideng is port ( clk : in std_logic; shift : in std_logic; q : out std_logic

13、_vector(3 downto 0);end;architecture shft_reg_arch of caideng issignal temp : std_logic_vector(3 downto 0);begin qtemptemptemptemptemptemptemptemptemptemptemptemptemptemptemptemptemptemp=0000; end case; end if; end if; end process ;end architecture真值表：STCLKQA10000010001110011310111701111F00111700011

14、3000011000000实验八：一、 设计一个同步带清零、带有进位输出端的模二十四计数器Library ieee;Use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;Entity count24 isPort(clk,clr:in std_logic; q0,q1,q2,q3,q4,q5:out std_logic);End;Architecture rtl of count24 isSignal count_6: std_logic_vector(5 downto 0);Begin q0=count_6(0); q1=co

15、unt_6(1); q2=count_6(2); q3=count_6(3); q4=count_6(4); q5=count_6(5); Process(clk) Begin if (clkevent and clk=1) then if clr=0 then count_6=000000; elsif count_6=100011 then count_6=000000; elsif count_6=001001 then count_6=010000; elsif count_6=011001 then count_6=100000; else count_6=count_6+1; en

16、d if; end if; End process;end;二、三、（1）：同步，文件名为bcd60countLIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity bcd60count isport(clk,bcd1wr,bcd10wr,cin: in std_logic; co: out std_logic; datain: in std_logic_vector(3 downto 0); bcd1p: out std_logic_vector(3 downto 0); bcd10p:

17、out std_logic_vector(2 downto 0);end bcd60count;architecture behave of bcd60count issignal bcd1n: std_logic_vector(3 downto 0);signal bcd10n: std_logic_vector(2 downto 0);begin bcd1p=bcd1n; bcd10p=bcd10n; kk1: process(clk,bcd1wr) begin if (bcd1wr=1) then bcd1n=datain; elsif(clkevent and clk=1) then

18、if (cin=1) then if(bcd1n=1001 ) then bcd1n=0000; else bcd1n=bcd1n+1; end if; end if; end if; end process kk1; kk2: process(clk,bcd10wr) begin if (bcd10wr=1) then bcd10n=datain(2 downto 0); elsif(clkevent and clk=1) then if(cin=1) and (bcd1n=1001) then if(bcd10n=101) then bcd10n=000; else bcd10n=bcd1

19、0n+1; end if; end if; end if; end process kk2;kk3: process(bcd10n,bcd1n,cin) begin if(cin=1 and bcd1n=1001 and bcd10n=101) then co=1; else co=0; end if; end process kk3; end behave;（2）异步：LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cou60 isport(clk,reset,cin : in s

20、td_logic; co : out std_logic; bcd1p : out std_logic_vector(3 downto 0); bcd10p : out std_logic_vector(2 downto 0);end cou60;architecture behave of cou60 issignal bcd1n: std_logic_vector(3 downto 0);signal bcd10n: std_logic_vector(2 downto 0);begin bcd1p=bcd1n; bcd10p=bcd10n; kk1: process(clk) begin

21、if(clkevent and clk=1) then if (reset=0) then bcd1n=0000; elsif (cin=1) then if(bcd1n=1001 ) then bcd1n=0000; else bcd1n=bcd1n+1; end if; end if; end if; end process kk1; kk2: process(clk) begin if(clkevent and clk=1) then if (reset=0) then bcd10n=101; elsif(cin=1) and (bcd1n=1001) then if(bcd10n=00

22、1) then bcd10n=101; else bcd10n=bcd10n+1; end if; end if; end if; end process kk2;kk3: process(bcd10n,bcd1n,cin) begin if(cin=1 and bcd1n=1001 and bcd10n=001) then co=1; else co=0; end if; end process kk3; end behave;四LIBRARY ieee;USE ieee.std_logic_1164.ALL; ENTITY piso ISPORT(DATA_IN :IN STD_LOGIC

23、_VECTOR(3 DOWNTO 0);CLK :IN STD_LOGIC;nLOAD :IN STD_LOGIC;DATA_OUT :OUT STD_LOGIC);END piso;ARCHITECTURE a OF piso ISSIGNAL Q: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(nLOAD,CLK)BEGINIF nLOAD = 0 THENQ = DATA_IN;ELSIF CLKEVENT AND CLK = 1 THENq(1) = Q(0) ;FOR I IN 1 TO 3 LOOPQ(I) = Q(I-1);END LOOP;END IF;END PROCESS; PROCESS(nLOAD,CLK)BEGINIF nLOAD = 0 THENDATA_OUT =