西安邮电学院数电eda实验 仿真.docx
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西安邮电学院数电eda实验仿真
实验五：
一、译码真值表
Libraryieee;
Useieee.std_logic_1164.all;
Entityqiduanis
Port（a:
instd_logic_vector（3downto0）;
y:
outstd_logic_vector（6downto0））;
End;
Architecturertlofqiduanis
Begin
Process（A）
Begin
CaseAis
When"0000"=>y<="1111110";
When"0001"=>y<="0110000";
When"0010"=>y<="1101101";
When"0011"=>y<="1111001";
When"0100"=>y<="0110011";
When"0101"=>y<="1011011";
When"0110"=>y<="1011111";
When"0111"=>y<="1110000";
When"1000"=>y<="1111111";
When"1001"=>y<="1111011";
When"1010"=>y<="1110111";
When"1011"=>y<="0011111";
When"1100"=>y<="1001110";
When"1101"=>y<="0111101";
When"1110"=>y<="1001111";
When"1111"=>y<="1000111";
Whenothers=>y<="ZZZZZZZ";
Endcase;
Endprocess;
End;
二、二进制数相乘的数码管显示
Libraryieee;
Useieee.std_logic_1164.all;
Entityshumaguanis
Port（a,b:
instd_logic_vector（1downto0）;
y:
outstd_logic_vector（6downto0））;
End;
Architecturertlofshumaguanis
Begin
Process（a,b）
Variablex:
std_logic_vector（3downto0）;
Begin
x:
=a&b;
CaseXis
When"0000"=>y<="1111110";
When"0001"=>y<="1111110";
When"0010"=>y<="1111110";
When"0011"=>y<="1111110";
When"0100"=>y<="1111110";
When"0101"=>y<="0110000";
When"0110"=>y<="1101101";
When"0111"=>y<="1111001";
When"1000"=>y<="1111110";
When"1001"=>y<="1101101";
When"1010"=>y<="0110011";
When"1011"=>y<="1011111";
When"1100"=>y<="1111110";
When"1101"=>y<="1111001";
When"1110"=>y<="1011111";
When"1111"=>y<="1111011";
Whenothers=>y<="ZZZZZZZ";
Endcase;
Endprocess;
End;
实验六
一、RS触发器
Libraryieee;
Useieee.std_logic_1164.all;
Entityrsff1is
Port（r,s,cp:
inbit;
q,qb:
bufferbit）;
End;
Architecturertlofrsff1is
Begin
qb<=（rnandcp）nandq;
q<=（snandcp）nandqb;
End;
二、JK触发器
Libraryieee;
Useieee.std_logic_1164.all;
Entityjkff1is
Port（j,k,clk,PRN,CLRN:
instd_logic;
q,qb:
outstd_logic）;
End;
Architecturertlofjkff1is
signalq_temp,qb_temp:
std_logic;
Begin
Process（clk,PRN,CLRN）
Begin
if（（PRNandCLRN）='0'）then
q_temp<=notPRN;
qb_temp<=PRN;
elsif（clk'eventandclk='1'）then
q_temp<=（jand（notq_temp））or（notkandq_temp）;
qb_temp<=notq_temp;
endif;
endprocess;
q<=q_temp;
qb<=qb_temp;
End;
三、D触发器
Libraryieee;
Useieee.std_logic_1164.all;
Entitydff1is
Port（d,clk,PRN,CLRN:
instd_logic;
q,qb:
outstd_logic）;
End;
Architecturertlofdff1is
signalq_temp,qb_temp:
std_logic;
Begin
Process（clk,PRN,CLRN）
Begin
if（（PRNandCLRN）='0'）then
q_temp<=notPRN;
qb_temp<=PRN;
elsif（clk'eventandclk='1'）then
q_temp<=d;
qb_temp<=notq_temp;
else
q_temp<=q_temp;
endif;
endprocess;
q<=q_temp;
qb<=qb_temp;
End;
四、开关控制电路设计
题3.19的真值表
ABCYABCY
00000110
00111010
01011100
10011111
Libraryieee;
Useieee.std_logic_1164.all;
Entitykaiguanis
Port（A,B,C:
instd_logic;
Y:
outstd_logic）;
End;
Architecturertlofkaiguanis
signalD,f0:
std_logic;
Begin
D<=AorBorC;
Process（D）
Begin
if（D'eventandD='1'）then
f0<=notf0;
endif;
Endprocess;
Y<=f0;
End;
实验七：
一、设计一位四位带异步清零的并入串出移位寄存器
LIBRARYieee;
USEieee.std_logic_1164.ALL;
ENTITYpisoIS
PORT（
DATA_IN:
INSTD_LOGIC_VECTOR（3DOWNTO0）;
CLK:
INSTD_LOGIC;
nLOAD:
INSTD_LOGIC;
DATA_OUT:
OUTSTD_LOGIC）;
ENDpiso;
ARCHITECTUREaOFpisoIS
SIGNALQ:
STD_LOGIC_VECTOR（3DOWNTO0）;
BEGIN
PROCESS（nLOAD,CLK）
BEGIN
IFnLOAD='0'THEN
Q<=DATA_IN;
ELSIFCLK'EVENTANDCLK='1'THEN
q
（1）<=Q（0）;
FORIIN1TO3LOOP
Q（I）<=Q（I-1）;
END LOOP;
ENDIF;
ENDPROCESS;
PROCESS（nLOAD,CLK）
BEGIN
IFnLOAD='0'THEN
DATA_OUT<='0';
ELSIFCLK'EVENTANDCLK='1'THEN
DATA_OUT<=Q（3）;
ENDIF;
ENDPROCESS;
ENDa;
二、环形计数器
libraryIEEE;
useIEEE.std_logic_1164.all;
entityhuanxingis
port（
clk:
instd_logic;
load:
instd_logic;
d:
instd_logic_vector（3downto0）;
q:
outstd_logic_vector（3downto0））;
end;
architectureshft_reg_archofhuanxingis
signalTEMP:
std_logic_vector（3downto0）;
begin
process（clk）
begin
ifclk'eventandclk='1'then
ifload='1'then
TEMP<=d;
elsifTEMP="1000"then
TEMP<=TEMP（0）&TEMP（3downto1）;
elsifTEMP="0100"then
TEMP<=TEMP（0）&TEMP（3downto1）;
elsifTEMP="0010"then
TEMP<=TEMP（0）&TEMP（3downto1）;
elsifTEMP="0001"then
TEMP<=TEMP（0）&TEMP（3downto1）;
elseTEMP<="1000";
endif;
endif;
endprocess;
q<=TEMP;
endarchitecture;
真值表：
CLK
Q
↑
1000
↑
0100
↑
0010
↑
0001
三、8位循环移位寄存器
其中D表示输入的初始值，Sta为开始移位信号，DOUT表示当前数值；LD表示预设计数值，LD为“1”，初始计数值打入器件；LR表示移位方向，LR为‘0’，循环右移位，LR为‘1’，循环左移位；CP为移位脉冲。
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYcyregIS
PORT（D:
INSTD_LOGIC_VECTOR（7DOWNTO0）;
LD:
INSTD_LOGIC;
LR:
INSTD_LOGIC;
CP:
INSTD_LOGIC;
DOUT:
BUFFERSTD_LOGIC_VECTOR（7DOWNTO0））;
ENDcyreg;
ARCHITECTUREsampleOFcyregIS
BEGIN
P1:
PROCESS（CP,LD）
BEGIN
ifLD='0'then
DOUT<=D;
elsifCP'EVENTANDCP='0'then
ifLR='1'then
DOUT<=DOUT（6DOWNTO0）&DOUT（7）;
elsifLR='0'then
DOUT<=DOUT（0）&DOUT（7DOWNTO1）;
endif;
endif;
ENDPROCESSP1;
ENDsample;
四、节日彩灯
libraryIEEE;
useIEEE.std_logic_1164.all;
entitycaidengis
port（
clk:
instd_logic;
shift:
instd_logic;
q:
outstd_logic_vector（3downto0））;
end;
architectureshft_reg_archofcaidengis
signaltemp:
std_logic_vector（3downto0）;
begin
q<=temp;
process（clk）
begin
if（clk'eventandclk='1'）then
ifshift='1'then
casetempis
when"0000"=>temp<="1000";
when"1000"=>temp<="1100";
when"1100"=>temp<="1110";
when"1110"=>temp<="1111";
when"1111"=>temp<="0111";
when"0111"=>temp<="0011";
when"0011"=>temp<="0001";
when"0001"=>temp<="0000";
whenothers=>temp<="0000";
endcase;
else
casetempis
when"0000"=>temp<="0001";
when"0001"=>temp<="0011";
when"0011"=>temp<="0111";
when"0111"=>temp<="1111";
when"1111"=>temp<="1110";
when"1110"=>temp<="1100";
when"1100"=>temp<="1000";
when"1000"=>temp<="0000";
whenothers=>temp<="0000";
endcase;
endif;
endif;
endprocess;
endarchitecture
真值表：
ST
CLK
Q
A
1
↑
0000
0
1
↑
0001
1
1
↑
0011
3
1
↑
0111
7
0
↑
1111
F
0
↑
0111
7
0
↑
0011
3
0
↑
0001
1
0
↑
0000
0
实验八：
一、设计一个同步带清零、带有进位输出端的模二十四计数器
Libraryieee;
Useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
Entitycount24is
Port（clk,clr:
instd_logic;
q0,q1,q2,q3,q4,q5:
outstd_logic）;
End;
Architecturertlofcount24is
Signalcount_6:
std_logic_vector（5downto0）;
Begin
q0<=count_6（0）;
q1<=count_6
（1）;
q2<=count_6
（2）;
q3<=count_6（3）;
q4<=count_6（4）;
q5<=count_6（5）;
Process（clk）
Begin
if（clk'eventandclk='1'）then
ifclr='0'then
count_6<="000000";
elsifcount_6="100011"then
count_6<="000000";
elsifcount_6="001001"then
count_6<="010000";
elsifcount_6="011001"then
count_6<="100000";
else
count_6<=count_6+'1';
endif;
endif;
Endprocess;
end;
二、
三、
（1）：
同步，文件名为bcd60count
LIBRARYieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitybcd60countis
port（clk,bcd1wr,bcd10wr,cin:
instd_logic;
co:
outstd_logic;
datain:
instd_logic_vector（3downto0）;
bcd1p:
outstd_logic_vector（3downto0）;
bcd10p:
outstd_logic_vector（2downto0））;
endbcd60count;
architecturebehaveofbcd60countis
signalbcd1n:
std_logic_vector（3downto0）;
signalbcd10n:
std_logic_vector（2downto0）;
begin
bcd1p<=bcd1n;
bcd10p<=bcd10n;
kk1:
process（clk,bcd1wr）
begin
if（bcd1wr='1'）then
bcd1n<=datain;
elsif（clk'eventandclk='1'）then
if（cin='1'）then
if（bcd1n="1001"）then
bcd1n<="0000";
else
bcd1n<=bcd1n+'1';
endif;
endif;
endif;
endprocesskk1;
kk2:
process（clk,bcd10wr）
begin
if（bcd10wr='1'）then
bcd10n<=datain（2downto0）;
elsif（clk'eventandclk='1'）then
if（cin='1'）and（bcd1n="1001"）then
if（bcd10n="101"）then
bcd10n<="000";
else
bcd10n<=bcd10n+'1';
endif;
endif;
endif;
endprocesskk2;
kk3:
process（bcd10n,bcd1n,cin）
begin
if（cin='1'andbcd1n="1001"andbcd10n="101"）then
co<='1';
else
co<='0';
endif;
endprocesskk3;
endbehave;
（2）异步：
LIBRARYieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycou60is
port（clk,reset,cin:
instd_logic;
co:
outstd_logic;
bcd1p:
outstd_logic_vector（3downto0）;
bcd10p:
outstd_logic_vector（2downto0））;
endcou60;
architecturebehaveofcou60is
signalbcd1n:
std_logic_vector（3downto0）;
signalbcd10n:
std_logic_vector（2downto0）;
begin
bcd1p<=bcd1n;
bcd10p<=bcd10n;
kk1:
process（clk）
begin
if（clk'eventandclk='1'）then
if（reset='0'）then
bcd1n<="0000";
elsif（cin='1'）then
if（bcd1n="1001"）then
bcd1n<="0000";
else
bcd1n<=bcd1n+'1';
endif;
endif;
endif;
endprocesskk1;
kk2:
process（clk）
begin
if（clk'eventandclk='1'）then
if（reset='0'）then
bcd10n<="101";
elsif（cin='1'）and（bcd1n="1001"）then
if（bcd10n="001"）then
bcd10n<="101";
else
bcd10n<=bcd10n+'1';
endif;
endif;
endif;
endprocesskk2;
kk3:
process（bcd10n,bcd1n,cin）
begin
if（cin='1'andbcd1n="1001"andbcd10n="001"）then
co<='1';
else
co<='0';
endif;
endprocesskk3;
endbehave;
四
LIBRARYieee;
USEieee.std_logic_1164.ALL;
ENTITYpisoIS
PORT（
DATA_IN:
INSTD_LOGIC_VECTOR（3DOWNTO0）;
CLK:
INSTD_LOGIC;
nLOAD:
INSTD_LOGIC;
DATA_OUT:
OUTSTD_LOGIC）;
ENDpiso;
ARCHITECTUREaOFpisoIS
SIGNALQ:
STD_LOGIC_VECTOR（3DOWNTO0）;
BEGIN
PROCESS（nLOAD,CLK）
BEGIN
IFnLOAD='0'THEN
Q<=DATA_IN;
ELSIFCLK'EVENTANDCLK='1'THEN
q
（1）<=Q（0）;
FORIIN1TO3LOOP
Q（I）<=Q（I-1）;
ENDLOOP;
ENDIF;
ENDPROCESS;
PROCESS（nLOAD,CLK）
BEGIN
IFnLOAD='0'THEN
DATA_OUT<='
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