1、vhdl实验报告16乘16点阵列选显示LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY XIANSHI ISPORT( res:IN STD_LOGIC; XUAN:IN STD_LOGIC_VECTOR(3 DOWNTO 0); SEL:IN STD_LOGIC_VECTOR(3 DOWNTO 0); Q:OUT STD_LOGIC_VECTOR(15 DOWNTO 0) );END ENTITY XIANSHI;ARCHITECTURE XSDZ OF XIANSHI ISBEGINPROCESS(XUAN,SEL,res)BEGINCASE
2、RES ISWHEN 1=CASE XUAN ISWHEN 0000=CASE SEL ISwhen 0000=QQQQQQQQQQQQQQQQnull;END CASE;WHEN 0001=CASE SEL ISwhen 0000=QQQQQQQQQQQQQQQQnull;END CASE;WHEN 0010=CASE SEL ISwhen 0000=QQQQQQQQQQQQQQQQnull;END CASE;WHEN 0011=CASE SEL ISwhen0000=QQQQQQQQQQQQQQQQnull;END CASE;WHEN 0100=CASE SEL ISwhen 0000=Q
3、QQQQQQQQQQQQQQQnull;END CASE;WHEN 0101=CASE SEL ISwhen0000=QQQQQQQQQQQQQQQQnull;END CASE;WHEN 0110=CASE SEL ISwhen 0000=QQQQQQQQQQQQQQQQnull;END CASE;WHEN 0111=CASE SEL ISwhen 0000=QQQQQQQQQQQQQQQQnull;END CASE;WHEN 1000=CASE SEL ISwhen 0000=QQQQQQQQQQQQQQQQnull;END CASE;WHEN 1001=CASE SEL ISwhen 00
4、00=QQQQQQQQQQQQQQQnull;END CASE;WHEN 1010=CASE SEL ISwhen 0000=QQQQQQQQQQQQQQQQnull;END CASE;WHEN 1011=CASE SEL ISwhen 0000=QQQQQQQQQQQQQQQQnull;END CASE;WHEN 1100=CASE SEL ISwhen 0000=QQQQQQQQQQQQQQQQnull;END CASE;WHEN 1101=CASE SEL ISwhen 0000=QQQQQQQQQQQQQQQQnull;END CASE;WHEN 1110=CASE SEL ISwhen 0000=QQQQQQQQQQQQ=1111111
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