硬件描述语言VHDL程序实例整理.docx

1、硬件描述语言VHDL程序实例整理硬件描述语言VHDL实例程序整理1.动态扫描显示程序library ieee;use ieee.std_logic_1164.all;entity dtsm_xs is port(clk:in std_logic; B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1:in std_logic_vector(3 downto 0); x:out std_logic_vector(6 downto 0); led_select: out std_logic_vector(13 downto 0);end;architectu

2、re behave of dtsm_xs issignal bcd_in: std_logic_vector (3 downto 0);signal cnt2: integer range 0 to 13;beginp1:process(clk) begin if clkevent and clk=1 then -升沿触发 if cnt2=13 then control loop cnt2=0; else cnt2led_select=11111111111110;bcd_inled_select=11111111111101;bcd_inled_select=11111111111011;b

3、cd_inled_select=11111111110111;bcd_inled_select=11111111101111;bcd_inled_select=11111111011111;bcd_inled_select=11111110111111;bcd_inled_select=11111101111111;bcd_inled_select=11111011111111;bcd_inled_select=11110111111111;bcd_inled_select=11101111111111;bcd_inled_select=11011111111111;bcd_inled_sel

4、ect=10111111111111;bcd_inled_select=01111111111111;bcd_inxxxxxxxxxxx=0000000; end case; end process;end;2.分频器设计程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;entity divider_1m isport(clk: in std_logic; clk_1Hz: out std_logic; clk_500Hz:buffer std_logic);end divider_1m;archit

5、ecture rtl of divider_1m issignal cnt1:integer range 0 to 1999;signal cnt2:integer range 0 to 499;beginp1:process(clk) begin if clkevent and clk=1 then if cnt1=cnt1high then cnt1=0; else cnt1=999 then clk_500Hz=1; else clk_500Hz=0; end if; end if; end process; p3:process(clk_500Hz) begin if clk_500H

6、zevent and clk_500Hz=1 then if cnt2=cnt2high then cnt2=0; else cnt2=249 then clk_1Hz=1; else clk_1Hz=0; end if; end if; end process; end rtl;3. 8位移位寄存器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY REG8 ISPORT(LOAD,CLR,DIRE,EN,CLK:IN STD_LOGIC; DATA :IN STD_LOGIC_VECTOR(7 DOWNTO 0); DOUT :BUFFER ST

7、D_LOGIC_VECTOR(7 DOWNTO 0);END REG8;ARCHITECTURE A OF REG8 IS BEGIN PROCESS(LOAD,CLR,DIRE,EN,CLK) VARIABLE X:STD_LOGIC; BEGIN IF LOAD=1 THEN DOUT=DATA; ELSIF CLR=1 THEN DOUT=00000000; ELSIF EN=1 THEN DOUT=DOUT; ELSIF CLKEVENT AND CLK=1 THEN IF DIRE=1THEN X:=DOUT(7); DOUT(7 DOWNTO 1)=DOUT(6 DOWNTO 0)

8、; DOUT(0)=X; ELSE X:=DOUT(0); DOUT(6 DOWNTO 0)=DOUT(7 DOWNTO 1); DOUT(7)=X; END IF; END IF;END IF; END PROCESS;END A;4.BCD计数器设计(任意进制)LIBRARY ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ENTITY cnt365 IS PORT(clk,reset:IN STD_LOGIC; daout:out std_logic_vector (9 downto 0);END;A

9、RCHITECTURE fun OF cnt365 IS SIGNAL count: STD_LOGIC_VECTOR(9 downto 0); BEGIN daout = count; p1:process(clk,reset) begin if (reset=1) then count = 0000000000; elsif (clkevent and clk=1) then if count(9 downto 0)=1101100100then count(9 downto 0)=0000000000; elsif count(7 downto 0)=10011001 then coun

10、t=count + 01100111; elsif count(3 downto 0)=1001 then count=count + 0111; else count = count + 1; end if; end if; end process p1; END fun;5.基于状态机的计数器设计library ieee;use ieee.std_logic_1164.all;entity statemachine_counter is port(clr,clk: in std_logic; q:out std_logic_vector(2 downto 0);end;architectu

11、re a of statemachine_counter istype state_type is (s0,s1,s2,s3,s4,s5,s6);signal present_state,next_state: state_type;beginp1:process(clk,clr)begin if clr=1 then present_state=s0; elsif clkevent and clk=1 then present_statenext_statenext_statenext_statenext_statenext_statenext_statenext_state=s0; end

12、 case; end process p2; p3:process(clr,present_state) begin if clr=1 then qqqqqqqq=110; end case; end if;end process p3;end a;6.LED灯控制-设计一个循环彩灯控制器-该控制器控制红，绿，黄三个发光二极管循环发亮-要求红发光管亮2秒，绿亮3秒，黄亮1秒。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ASM_LED ISPORT( CLR: IN STD_LOGIC; -清零控制输入 CLK: IN STD_LOGIC; -

13、时钟输入 LED1:OUT STD_LOGIC; -LED1输出 LED2:OUT STD_LOGIC; -LED2输出 LED3:OUT STD_LOGIC); -LED3输出END ASM_LED; -实体名称可以省略-ARCHITECTURE A OF ASM_LED ISTYPE STATE_TYPE IS (S0,S1,S2,S3,S4,S5,S6); -枚举类型，状态SIGNAL PRESENT_STATE,NEXT_STATE: STATE_TYPE; -定义信号BEGIN - P1:PROCESS(CLK,CLR) -进程1，判断时钟端与清零端，从而得到当前状态 BEGIN -

14、开始 IF CLR=1 THEN -如果清零端有效 PRESENT_STATE=S0; -当前状态就为S0 ELSIF CLKEVENT AND CLK=1 THEN -如果有上升沿到来 PRESENT_STATE NEXT_STATE NEXT_STATE NEXT_STATE NEXT_STATE NEXT_STATE NEXT_STATE NEXT_STATE=S1; END CASE; END PROCESS P2; - P3:PROCESS(CLR,PRESENT_STATE) -进程3 BEGIN IF CLR=1 THEN LED1=0;LED2=0;LED3 LED1=0;LE

15、D2=0;LED3 LED1=1;LED2=0;LED3 LED1=0;LED2=1;LED3 LED1=0;LED2=1;LED3 LED1=0;LED2=0;LED3 LED1=0;LED2=0;LED3 LED1=0;LED2=0;LED3doutdoutdoutdoutdoutdoutdoutdoutdoutdoutdoutnull; end case;end process;end rtl;8.100M频率计设计LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY FREQUEN

16、CY_TEST ISPORT(FSIN:IN STD_LOGIC; CLK:IN STD_LOGIC; DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0);END FREQUENCY_TEST;ARCHITECTURE BEHAVE OF FREQUENCY_TEST ISSIGNAL TEST_EN:STD_LOGIC;SIGNAL CLEAR:STD_LOGIC;SIGNAL DATA:STD_LOGIC_VECTOR(31 DOWNTO 0);BEGIN PROCESS(CLK) BEGIN IF CLKEVENT AND CLK=1 THEN TEST_EN=

17、NOT TEST_EN; END IF; END PROCESS; CLEAR=NOT CLK AND NOT TEST_EN; PROCESS(FSIN) BEGIN IF CLEAR=1 THEN DATA=00000000000000000000000000000000; ELSIF FSINEVENT AND FSIN=1 THEN IF DATA(31 DOWNTO 0)=10011001100110011001100110011001 THEN DATA=DATA+01100110011001100110011001100111; ELSIF DATA(27 DOWNTO 0)=1

18、001100110011001100110011001 THEN DATA=DATA+0110011001100110011001100111; ELSIF DATA(23 DOWNTO 0)=100110011001100110011001 THEN DATA=DATA+011001100110011001100111; ELSIF DATA(19 DOWNTO 0)=10011001100110011001 THEN DATA=DATA+01100110011001100111; ELSIF DATA(15 DOWNTO 0)=1001100110011001 THEN DATA=DATA

19、+0110011001100111; ELSIF DATA(11 DOWNTO 0)=100110011001 THEN DATA=DATA+011001100111; ELSIF DATA(7 DOWNTO 0)=10011001 THEN DATA=DATA+01100111; ELSIF DATA(3 DOWNTO 0)=1001 THEN DATA=DATA+0111; ELSE DATA=DATA+1; END IF; END IF; END PROCESS; PROCESS(TEST_EN,DATA) BEGIN IF TEST_ENEVENT AND TEST_EN=0 THEN DOUT=DATA; END IF; END PROCESS;END BEHAVE;