硬件描述语言VHDL程序实例整理.docx
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硬件描述语言VHDL程序实例整理
硬件描述语言VHDL实例程序整理
1.动态扫描显示程序
libraryieee;
useieee.std_logic_1164.all;
entitydtsm_xsis
port（clk:
instd_logic;
B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1:
instd_logic_vector（3downto0）;
x:
outstd_logic_vector（6downto0）;
led_select:
outstd_logic_vector（13downto0））;
end;
architecturebehaveofdtsm_xsis
signalbcd_in:
std_logic_vector（3downto0）;
signalcnt2:
integerrange0to13;
begin
p1:
process（clk）
begin
ifclk'eventandclk='1'then--升沿触发
ifcnt2>=13then–controlloop
cnt2<=0;
else
cnt2<=cnt2+1;
endif;
endif;
endprocess;
p2:
process（cnt2,B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1）
begin
casecnt2is
when0=>led_select<="11111111111110";bcd_in<=B1;
when1=>led_select<="11111111111101";bcd_in<=B2;
when2=>led_select<="11111111111011";bcd_in<=B3;
when3=>led_select<="11111111110111";bcd_in<=B4;
when4=>led_select<="11111111101111";bcd_in<=B5;
when5=>led_select<="11111111011111";bcd_in<=B6;
when6=>led_select<="11111110111111";bcd_in<=B7;
when7=>led_select<="11111101111111";bcd_in<=B8;
when8=>led_select<="11111011111111";bcd_in<=B9;
when9=>led_select<="11110111111111";bcd_in<=B10;
when10=>led_select<="11101111111111";bcd_in<=B11;
when11=>led_select<="11011111111111";bcd_in<=B12;
when12=>led_select<="10111111111111";bcd_in<=B13;
when13=>led_select<="01111111111111";bcd_in<=B14;
endcase;
endprocess;
p3:
process（bcd_in）
begin
casebcd_inis
when"0000"=>x<="1111110";
when"0001"=>x<="0110000";
when"0010"=>x<="1101101";
when"0011"=>x<="1111001";
when"0100"=>x<="0110011";
when"0101"=>x<="1011011";
when"0110"=>x<="1011111";
when"0111"=>x<="1110000";
when"1000"=>x<="1111111";
when"1001"=>x<="1111011";
whenothers=>x<="0000000";
endcase;
endprocess;
end;
2.分频器设计程序
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
entitydivider_1mis
port（clk:
instd_logic;
clk_1Hz:
outstd_logic;
clk_500Hz:
bufferstd_logic）;
enddivider_1m;
architecturertlofdivider_1mis
signalcnt1:
integerrange0to1999;
signalcnt2:
integerrange0to499;
begin
p1:
process（clk）
begin
ifclk'eventandclk='1'then
ifcnt1=cnt1'highthen
cnt1<=0;
else
cnt1<=cnt1+1;
endif;
endif;
endprocess;
p2:
process（clk,cnt1）
begin
ifclk'eventandclk='1'then
ifcnt1>=999then
clk_500Hz<='1';
else
clk_500Hz<='0';
endif;
endif;
endprocess;
p3:
process（clk_500Hz）
begin
ifclk_500Hz'eventandclk_500Hz='1'then
ifcnt2=cnt2'highthen
cnt2<=0;
else
cnt2<=cnt2+1;
endif;
endif;
endprocess;
p4:
process（clk_500Hz,cnt2）
begin
ifclk_500Hz'eventandclk_500Hz='1'then
ifcnt2>=249then
clk_1Hz<='1';
else
clk_1Hz<='0';
endif;
endif;
endprocess;
endrtl;
3.8位移位寄存器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYREG8IS
PORT（LOAD,CLR,DIRE,EN,CLK:
INSTD_LOGIC;
DATA:
INSTD_LOGIC_VECTOR（7DOWNTO0）;
DOUT:
BUFFERSTD_LOGIC_VECTOR（7DOWNTO0））;
ENDREG8;
ARCHITECTUREAOFREG8IS
BEGIN
PROCESS（LOAD,CLR,DIRE,EN,CLK）
VARIABLEX:
STD_LOGIC;
BEGIN
IFLOAD='1'THENDOUT<=DATA;
ELSIFCLR='1'THENDOUT<="00000000";
ELSIFEN='1'THENDOUT<=DOUT;
ELSIFCLK'EVENTANDCLK='1'THEN
IFDIRE='1'THEN
X:
=DOUT（7）;
DOUT（7DOWNTO1）<=DOUT（6DOWNTO0）;
DOUT（0）<=X;
ELSE
X:
=DOUT（0）;
DOUT（6DOWNTO0）<=DOUT（7DOWNTO1）;
DOUT（7）<=X;
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
ENDA;
4.BCD计数器设计（任意进制）
LIBRARYieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
ENTITYcnt365IS
PORT（clk,reset:
INSTD_LOGIC;
daout:
outstd_logic_vector（9downto0））;
END;
ARCHITECTUREfunOFcnt365IS
SIGNALcount:
STD_LOGIC_VECTOR（9downto0）;
BEGIN
daout<=count;
p1:
process（clk,reset）
begin
if（reset='1'）then
count<="0000000000";
elsif（clk'eventandclk='1'）then
ifcount（9downto0）="1101100100"then
count（9downto0）<="0000000000";
elsifcount（7downto0）="10011001"then
count<=count+"01100111";
elsifcount（3downto0）="1001"then
count<=count+"0111";
else
count<=count+1;
endif;
endif;
endprocessp1;
ENDfun;
5.基于状态机的计数器设计
libraryieee;
useieee.std_logic_1164.all;
entitystatemachine_counteris
port（clr,clk:
instd_logic;
q:
outstd_logic_vector（2downto0））;
end;
architectureaofstatemachine_counteris
typestate_typeis（s0,s1,s2,s3,s4,s5,s6）;
signalpresent_state,next_state:
state_type;
begin
p1:
process（clk,clr）
begin
ifclr='1'then
present_state<=s0;
elsifclk'eventandclk='1'then
present_state<=next_state;
endif;
endprocessp1;
p2:
process（clk,present_state）
begin
casepresent_stateis
whens0=>next_state<=s1;
whens1=>next_state<=s2;
whens2=>next_state<=s3;
whens3=>next_state<=s4;
whens4=>next_state<=s5;
whens5=>next_state<=s6;
whens6=>next_state<=s0;
endcase;
endprocessp2;
p3:
process（clr,present_state）
begin
ifclr='1'then
q<="000";
else
casepresent_stateis
whens0=>q<="000";
whens1=>q<="001";
whens2=>q<="010";
whens3=>q<="011";
whens4=>q<="100";
whens5=>q<="101";
whens6=>q<="110";
endcase;
endif;
endprocessp3;
enda;
6.LED灯控制
--设计一个循环彩灯控制器
--该控制器控制红，绿，黄三个发光二极管循环发亮
--要求红发光管亮2秒，绿亮3秒，黄亮1秒。
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYASM_LEDIS
PORT（CLR:
INSTD_LOGIC;--清零控制输入
CLK:
INSTD_LOGIC;--时钟输入
LED1:
OUTSTD_LOGIC;--LED1输出
LED2:
OUTSTD_LOGIC;--LED2输出
LED3:
OUTSTD_LOGIC）;--LED3输出
ENDASM_LED;--实体名称可以省略
---------------------------------------------
ARCHITECTUREAOFASM_LEDIS
TYPESTATE_TYPEIS（S0,S1,S2,S3,S4,S5,S6）;--枚举类型，状态
SIGNALPRESENT_STATE,NEXT_STATE:
STATE_TYPE;--定义信号
BEGIN
----------------------------------
P1:
PROCESS（CLK,CLR）--进程1，判断时钟端与清零端，从而得到当前状态
BEGIN--开始
IFCLR='1'THEN--如果清零端有效
PRESENT_STATE<=S0;--当前状态就为S0
ELSIFCLK'EVENTANDCLK='1'THEN--如果有上升沿到来
PRESENT_STATE<=NEXT_STATE;--当前状态就变为下一个状态
ENDIF;
ENDPROCESSP1;
---------------------------------------
P2:
PROCESS（CLK,PRESENT_STATE）--进程2，
BEGIN
CASEPRESENT_STATEIS
WHENS0=>
NEXT_STATE<=S1;
WHENS1=>
NEXT_STATE<=S2;
WHENS2=>
NEXT_STATE<=S3;
WHENS3=>
NEXT_STATE<=S4;
WHENS4=>
NEXT_STATE<=S5;
WHENS5=>
NEXT_STATE<=S6;
WHENS6=>
NEXT_STATE<=S1;
ENDCASE;
ENDPROCESSP2;
--------------------------------------
P3:
PROCESS（CLR,PRESENT_STATE）--进程3
BEGIN
IFCLR='1'THEN
LED1<='0';LED2<='0';LED3<='0';
ELSE
CASEPRESENT_STATEIS
WHENS0=>
LED1<='0';LED2<='0';LED3<='0';
WHENS1=>
LED1<='1';LED2<='0';LED3<='0';--LED1（黄色发光管点亮1秒）
WHENS2=>
LED1<='0';LED2<='1';LED3<='0';--LED2（红色发光管点亮2秒）
WHENS3=>
LED1<='0';LED2<='1';LED3<='0';
WHENS4=>
LED1<='0';LED2<='0';LED3<='1';--LED3（绿色发光管点亮3秒）
WHENS5=>
LED1<='0';LED2<='0';LED3<='1';
WHENS6=>
LED1<='0';LED2<='0';LED3<='1';
ENDCASE;
ENDIF;
ENDPROCESSP3;
ENDA;
7.BCD显示译码器
libraryieee;
useieee.std_logic_1164.all;
entitydecoder7is
port（bcd:
instd_logic_vector（3downto0）;
dout:
outstd_logic_vector（6downto0））;
enddecoder7;
architecturertlofdecoder7is
begin
process（bcd）
begin
casebcdis
whenb"0000"=>dout<=b"0111111";
whenb"0001"=>dout<=b"0000110";
whenb"0010"=>dout<=b"1011011";
whenb"0011"=>dout<=b"1001111";
whenb"0100"=>dout<=b"1100110";
whenb"0101"=>dout<=b"1101101";
whenb"0110"=>dout<=b"1111101";
whenb"0111"=>dout<=b"0000111";
whenb"1000"=>dout<=b"1111111";
whenb"1001"=>dout<=b"1101111";
whenothers=>dout<="0000000";
whenothers=>null;
endcase;
endprocess;
endrtl;
8.100M频率计设计
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYFREQUENCY_TESTIS
PORT（FSIN:
INSTD_LOGIC;
CLK:
INSTD_LOGIC;
DOUT:
OUTSTD_LOGIC_VECTOR（31DOWNTO0））;
ENDFREQUENCY_TEST;
ARCHITECTUREBEHAVEOFFREQUENCY_TESTIS
SIGNALTEST_EN:
STD_LOGIC;
SIGNALCLEAR:
STD_LOGIC;
SIGNALDATA:
STD_LOGIC_VECTOR（31DOWNTO0）;
BEGIN
PROCESS（CLK）
BEGIN
IFCLK'EVENTANDCLK='1'THEN
TEST_EN<=NOTTEST_EN;
ENDIF;
ENDPROCESS;
CLEAR<=NOTCLKANDNOTTEST_EN;
PROCESS（FSIN）
BEGIN
IFCLEAR='1'THEN
DATA<="00000000000000000000000000000000";
ELSIFFSIN'EVENTANDFSIN='1'THEN
IFDATA（31DOWNTO0）="10011001100110011001100110011001"THEN
DATA<=DATA+"01100110011001100110011001100111";
ELSIFDATA（27DOWNTO0）="1001100110011001100110011001"THEN
DATA<=DATA+"0110011001100110011001100111";
ELSIFDATA（23DOWNTO0）="100110011001100110011001"THEN
DATA<=DATA+"011001100110011001100111";
ELSIFDATA（19DOWNTO0）="10011001100110011001"THEN
DATA<=DATA+"01100110011001100111";
ELSIFDATA（15DOWNTO0）="1001100110011001"THEN
DATA<=DATA+"0110011001100111";
ELSIFDATA（11DOWNTO0）="100110011001"THEN
DATA<=DATA+"011001100111";
ELSIFDATA（7DOWNTO0）="10011001"THEN
DATA<=DATA+"01100111";
ELSIFDATA（3DOWNTO0）="1001"THEN
DATA<=DATA+"0111";
ELSE
DATA<=DATA+'1';
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS（TEST_EN,DATA）
BEGIN
IFTEST_EN'EVENTANDTEST_EN='0'THEN
DOUT<=DATA;
ENDIF;
ENDPROCESS;
ENDBEHAVE;
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