基于FPGA的即时通讯工具.docx

1、基于FPGA的即时通讯工具基于FPGA的即时通讯工具 成员：赵志强，王再成，宫盐坤，高彩丽 成员: 马超，孙建永，张鹏日期：2011年1月1日组内分工PS2键盘输入赵志强，王再成，宫盐坤，高彩丽LCD显示孙建永，张鹏Uart通信马超各模块整合孙建永，张鹏代码：ps2键盘上输入(赵志强，王再成，宫盐坤，高彩丽)module ps2_scan( clk, rst_n, ps2_clk, ps2_data, data_out_8bit, ps2_state, valid_flag); input clk; input rst_n; input ps2_clk; /PS2接口时钟信号input ps2

2、_data; /PS2接口数据信号output7:0 data_out_8bit;/ 1byte键值只做简单的按键扫描output ps2_state; /键盘当前状态ps2_state=1表示有键被按下output valid_flag;/reg 7:0 data_out_8bit;/*reg ps2_clk1,ps2_clk2,ps2_clk3; always (posedge clk or negedge rst_n) if(rst_n) begin ps2_clk1 = 1b0; ps2_clk2 = 1b0; ps2_clk3 = 1b0; end else begin ps2_cl

3、k1 = ps2_clk; ps2_clk2 = ps2_clk1; ps2_clk3 = ps2_clk2; end wire neg_clkps2; assign neg_clkps2=ps2_clk2 & ps2_clk3;/*reg ps2_state; reg7:0 ps2_byte_r; reg7:0 temp_data;reg 3:0 num; /当前接收数据寄存?reg3:0 num; always (posedge clk or negedge rst_n) begin if(!rst_n) begin num = 4d0; temp_data = 8d0; ps2_stat

4、e = 1b0; end else if(neg_clkps2) begin /ps2k_clk的下降沿接收键盘数据 case (num) 4d0: begin num = num+1b1; ps2_state = 1b1; end 4d1: begin num = num+1b1; temp_data0 = ps2_data; /bit0 end 4d2: begin num = num+1b1; temp_data1 = ps2_data; /bit1 end 4d3: begin num = num+1b1; temp_data2 = ps2_data; /bit2 end 4d4: b

5、egin num = num+1b1; temp_data3 = ps2_data; /bit3 end 4d5: begin num = num+1b1; temp_data4 = ps2_data; /bit4 end 4d6: begin num = num+1b1; temp_data5 = ps2_data; /bit5 end 4d7: begin num = num+1b1; temp_data6 = ps2_data; /bit6 end 4d8: begin num = num+1b1; temp_data7 = ps2_data; /bit7 end 4d9: num =

6、num+1b1; /奇偶校验位不做处理 4d10: begin num = 4d0; ps2_state = 1b0; end default: begin num = 4d0; temp_data = 8d0; ps2_state = 1b0; end endcase endend/*reg key_f0; reg reg_valid_flag;always (posedge clk or negedge rst_n) if(!rst_n) begin key_f0 = 1b0; reg_valid_flag = 1b0; end else begin if(num=4d10) begin

7、/刚传送完一个字节数据 if(temp_data = 8hf0) begin key_f0 = 1b1; reg_valid_flag = 1b1; end else begin if(key_f0) begin ps2_byte_r = temp_data; /锁存当前键值 reg_valid_flag = 1b0; end else begin key_f0 = 1b0; reg_valid_flag = 1b0; end end end else begin reg_valid_flag = 1b0; end end /*reg7:0 ps2_asci; /接SCII码always (p

8、s2_byte_r) begin case (ps2_byte_r) /键值转换为ASCII码 8h15: ps2_asci = 8h51; /Q 8h1d: ps2_asci = 8h57; /W 8h24: ps2_asci = 8h45; /E 8h2d: ps2_asci = 8h52; /R 8h2c: ps2_asci = 8h54; /T 8h35: ps2_asci = 8h59; /Y 8h3c: ps2_asci = 8h55; /U 8h43: ps2_asci = 8h49; /I 8h44: ps2_asci = 8h4f; /O 8h4d: ps2_asci = 8

9、h50; /P 8h1c: ps2_asci = 8h41; /A 8h1b: ps2_asci = 8h53; /S 8h23: ps2_asci = 8h44; /D 8h2b: ps2_asci = 8h46; /F 8h34: ps2_asci = 8h47; /G 8h33: ps2_asci = 8h48; /H 8h3b: ps2_asci = 8h4a; /J 8h42: ps2_asci = 8h4b; /K 8h4b: ps2_asci = 8h4c; /L 8h1z: ps2_asci = 8h5a; /Z 8h22: ps2_asci = 8h58; /X 8h21:

10、ps2_asci = 8h43; /C 8h2a: ps2_asci = 8h56; /V 8h32: ps2_asci = 8h42; /B 8h31: ps2_asci = 8h4e; /N 8h3a: ps2_asci = 8h4d; /M 8h16: ps2_asci = 8h31; /1 8h1E: ps2_asci = 8h32; /2 8h26: ps2_asci = 8h33; /3 8h25: ps2_asci = 8h34; /4 8h2E: ps2_asci = 8h35; /5 8h36: ps2_asci = 8h36; /6 8h3D: ps2_asci = 8h3

11、7; /7 8h3E: ps2_asci = 8h38; /8 8h46: ps2_asci = 8h39; /9 8h45: ps2_asci = 8h30; /0 8h5A: ps2_asci = 8h0D; /Enter default: ps2_asci = 8h00; endcaseend reg prev_valid_sig_0; reg prev_valid_sig_1; always (posedge clk) begin prev_valid_sig_0 = reg_valid_flag; prev_valid_sig_1 = prev_valid_sig_0; end re

12、g valid_flag; /assign valid_flag = prev_valid_sig_0 & prev_valid_sig_1; always (posedge clk) begin if(valid_flag = 1b1) begin valid_flag = 1b0; end else valid_flag =prev_valid_sig_0 & prev_valid_sig_1; end assign data_out_8bit = ps2_asci; endmoduleLCD显示（孙建永，张鹏）：module lcd(sf_d, lcd_e, lcd_rs, lcd_rw

13、, rst, clk, state, idle_h, if_write, data_input_8bit); input rst; input clk; input if_write; input 7:0 data_input_8bit; output idle_h; output lcd_e; output lcd_rs; output lcd_rw; output 3:0 sf_d; output 5:0 state; reg lcd_e; reg lcd_rs; reg lcd_rw; reg 3:0 sf_d; reg idle_h; parameter data_stable_wai

14、t = 2, lcd_e_h_wait = 12, inter_wait = 50, sta_between_wait = 2000, after_init_wait = 2000, after_cln_dis_wait = 92000, sta_begin_wait = 750000, sta_init_1_wait = 205000, sta_init_2_wait = 5000, sta_init_3_wait = 2000, sta_init_4_wait = 2000; parameter sta_begin = 6b00_0000, sta_init_1_1= 6b00_0001,

15、 sta_init_1_begin_lcd_e_h_wait = 6b00_0010, sta_init_1_end = 6b00_0011, sta_init_2_begin = 6b00_0100, sta_init_2_end = 6b00_0101, sta_init_3_begin = 6b00_0110, sta_init_3_end = 6b00_0111, sta_init_4_begin = 6b00_1000, sta_init_4_lcd_e_h_wait = 6b00_1001, sta_after_init_4_wait = 6b00_1010, sta_functi

16、on_set_1 = 6b00_1011, sta_function_set_1_lcd_e_h_wait = 6b00_1100, sta_function_set_inter_wait = 6b00_1101, sta_function_set_2 = 6b00_1110, sta_function_set_2_lcd_e_h_wait = 6b00_1111, sta_after_function_set_wait = 6b01_0000, sta_entry_mode_set_1 = 6b01_0001, sta_entry_mode_set_1_lcd_e_h_wait = 6b01

17、_0010, sta_entry_mode_set_inter_wait = 6b01_0011, sta_entry_mode_set_2 = 6b01_0100, sta_entry_mode_set_2_lcd_e_h_wait = 6b01_0101, sta_after_entry_mode_set_wait = 6b01_0110, sta_dis_on_off_1 = 6b01_0111, sta_dis_on_off_1_lcd_e_h_wait = 6b01_1000, sta_dis_on_off_inter_wait = 6b01_1001, sta_dis_on_off

18、_2 = 6b01_1010, sta_dis_on_off_lcd_e_h_wait = 6b01_1011, sta_after_dis_on_off = 6b01_1100, sta_cln_dis_1 = 6b01_1101, sta_cln_dis_1_lcd_e_h_wait = 6b01_1110, sta_cln_dis_inter_wait = 6b01_1111, sta_cln_dis_2 = 6b10_0000, sta_cln_dis_2_lcd_e_h_wait = 6b10_0001, sta_after_cln_dis_wait = 6b10_0010, sta

19、_write_addr_1 = 6b10_0011, sta_write_addr_1_lcd_e_h_wait = 6b10_0100, sta_write_addr_inter_wait = 6b10_0101, sta_write_addr_2 = 6b10_0110, sta_write_addr_2_lcd_e_h_wait = 6b10_0111, sta_after_write_addr = 6b10_1000, sta_write_data_1 = 6b10_1001, sta_write_data_1_lcd_e_h_wait = 6b10_1010, sta_write_d

20、ata_inter_wait = 6b10_1011, sta_write_data_2 = 6b10_1100, sta_write_data_2_lcd_e_h_wait = 6b10_1101, sta_write_idle = 6b10_1110, sta_write_begin = 6b10_1111, sta_write_end_wait = 6b11_0000, sta_detect_data = 6b11_0001; parameter SET_HIGH_ADDR = 8b1000_0000, SET_LOW_ADDR = 8b1100_0000, CLN = 8b1111_1

21、100; reg 5:0 state; reg 19:0 cnt; reg 7:0 data_write_8bit; always (posedge clk) begin lcd_rw = 1b0; end always (posedge clk or negedge rst) begin if(rst = 1b0) begin state = sta_begin; lcd_rs = 1b0; cnt = 0; idle_h = 1b0; end else begin case (state) sta_begin:begin if(cnt = sta_begin_wait)begin cnt

22、= 0; state = sta_function_set_1; idle_h = 1b0; end else cnt = cnt + 1; end sta_function_set_1:begin if(cnt = data_stable_wait) begin lcd_e = 1b1; state = sta_function_set_1_lcd_e_h_wait; cnt = 0; end else begin cnt = cnt + 1; sf_d = 4b0010; lcd_rs = 1b0; end end sta_function_set_1_lcd_e_h_wait: begi

23、n if(cnt = lcd_e_h_wait) begin state = sta_function_set_inter_wait; lcd_e = 1b0; cnt = 0; end else cnt = cnt + 1; end sta_function_set_inter_wait:begin if(cnt = inter_wait) begin state = sta_function_set_2; cnt = 0; end else cnt = cnt + 1; end sta_function_set_2: begin if(cnt = data_stable_wait) beg

24、in lcd_e = 1b1; state = sta_function_set_2_lcd_e_h_wait; cnt = 0; end else begin cnt = cnt + 1; sf_d = 4b1000; end end sta_function_set_2_lcd_e_h_wait: begin if(cnt = lcd_e_h_wait) begin state = sta_after_function_set_wait; lcd_e = 1b0; cnt = 0; end else cnt = cnt + 1; end sta_after_function_set_wai

25、t: begin if(cnt = sta_between_wait) begin state = sta_entry_mode_set_1; cnt = 0; end else cnt = cnt + 1; end sta_entry_mode_set_1:begin if(cnt = data_stable_wait) begin state = sta_entry_mode_set_1_lcd_e_h_wait; lcd_e = 1b1; cnt = 0; end else begin cnt = cnt + 1; sf_d = 4b0000; end end sta_entry_mod

26、e_set_1_lcd_e_h_wait:begin if(cnt = lcd_e_h_wait) begin state = sta_entry_mode_set_inter_wait; lcd_e = 1b0; cnt = 0; end else cnt = cnt + 1; end sta_entry_mode_set_inter_wait: begin if(cnt = inter_wait) begin state = sta_entry_mode_set_2; cnt = 0; end else cnt = cnt + 1; end sta_entry_mode_set_2: begin if(cnt = data_stable_wait) begin state = sta_entry_mode_set_2_lcd_e_h_wait; lcd_e = 1b1; cnt = 0; end else begin cnt = cnt + 1; sf_d = 4b0110; end end sta_entry_mode_set_2_lcd_e_h_wait: begin if(cnt = lcd_e